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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3 TWI definitions.
39 /** I2C registers base. */
41 #define TWI0_BASE 0x4008C000
42 #define TWI1_BASE 0x40090000
44 #error TWI registers not defined for selected CPU
49 * TWI register offsets.
52 #define TWI_CR_OFF 0x000
53 #define TWI_MMR_OFF 0x004
54 #define TWI_SMR_OFF 0x008
55 #define TWI_IADR_OFF 0x00C
56 #define TWI_CWGR_OFF 0x010
57 #define TWI_SR_OFF 0x020
58 #define TWI_IER_OFF 0x024
59 #define TWI_IDR_OFF 0x028
60 #define TWI_IMR_OFF 0x02C
61 #define TWI_RHR_OFF 0x030
62 #define TWI_THR_OFF 0x034
63 #define TWI_RPR_OFF 0x100
64 #define TWI_RCR_OFF 0x104
65 #define TWI_TPR_OFF 0x108
66 #define TWI_TCR_OFF 0x10C
67 #define TWI_RNPR_OFF 0x110
68 #define TWI_RNCR_OFF 0x114
69 #define TWI_TNPR_OFF 0x118
70 #define TWI_TNCR_OFF 0x11C
71 #define TWI_PTCR_OFF 0x120
72 #define TWI_PTSR_OFF 0x124
80 #define TWI_CR (HWREG(TWI_BASE + TWI_CR_OFF))
81 #define TWI_MMR (HWREG(TWI_BASE + TWI_MMR_OFF))
82 #define TWI_SMR (HWREG(TWI_BASE + TWI_SMR_OFF))
83 #define TWI_IADR (HWREG(TWI_BASE + TWI_IADR_OFF))
84 #define TWI_CWGR (HWREG(TWI_BASE + TWI_CWGR_OFF))
85 #define TWI_SR (HWREG(TWI_BASE + TWI_SR_OFF))
86 #define TWI_IER (HWREG(TWI_BASE + TWI_IER_OFF))
87 #define TWI_IDR (HWREG(TWI_BASE + TWI_IDR_OFF))
88 #define TWI_IMR (HWREG(TWI_BASE + TWI_IMR_OFF))
89 #define TWI_RHR (HWREG(TWI_BASE + TWI_RHR_OFF))
90 #define TWI_THR (HWREG(TWI_BASE + TWI_THR_OFF))
91 #define TWI_RPR (HWREG(TWI_BASE + TWI_RPR_OFF))
92 #define TWI_RCR (HWREG(TWI_BASE + TWI_RCR_OFF))
93 #define TWI_TPR (HWREG(TWI_BASE + TWI_TPR_OFF))
94 #define TWI_TCR (HWREG(TWI_BASE + TWI_TCR_OFF))
95 #define TWI_RNPR (HWREG(TWI_BASE + TWI_RNPR_OFF))
96 #define TWI_RNCR (HWREG(TWI_BASE + TWI_RNCR_OFF))
97 #define TWI_TNPR (HWREG(TWI_BASE + TWI_TNPR_OFF))
98 #define TWI_TNCR (HWREG(TWI_BASE + TWI_TNCR_OFF))
99 #define TWI_PTCR (HWREG(TWI_BASE + TWI_PTCR_OFF))
100 #define TWI_PTSR (HWREG(TWI_BASE + TWI_PTSR_OFF))
104 #define TWI0_CR (HWREG(TWI0_BASE + TWI_CR_OFF))
105 #define TWI0_MMR (HWREG(TWI0_BASE + TWI_MMR_OFF))
106 #define TWI0_SMR (HWREG(TWI0_BASE + TWI_SMR_OFF))
107 #define TWI0_IADR (HWREG(TWI0_BASE + TWI_IADR_OFF))
108 #define TWI0_CWGR (HWREG(TWI0_BASE + TWI_CWGR_OFF))
109 #define TWI0_SR (HWREG(TWI0_BASE + TWI_SR_OFF))
110 #define TWI0_IER (HWREG(TWI0_BASE + TWI_IER_OFF))
111 #define TWI0_IDR (HWREG(TWI0_BASE + TWI_IDR_OFF))
112 #define TWI0_IMR (HWREG(TWI0_BASE + TWI_IMR_OFF))
113 #define TWI0_RHR (HWREG(TWI0_BASE + TWI_RHR_OFF))
114 #define TWI0_THR (HWREG(TWI0_BASE + TWI_THR_OFF))
115 #define TWI0_RPR (HWREG(TWI0_BASE + TWI_RPR_OFF))
116 #define TWI0_RCR (HWREG(TWI0_BASE + TWI_RCR_OFF))
117 #define TWI0_TPR (HWREG(TWI0_BASE + TWI_TPR_OFF))
118 #define TWI0_TCR (HWREG(TWI0_BASE + TWI_TCR_OFF))
119 #define TWI0_RNPR (HWREG(TWI0_BASE + TWI_RNPR_OFF))
120 #define TWI0_RNCR (HWREG(TWI0_BASE + TWI_RNCR_OFF))
121 #define TWI0_TNPR (HWREG(TWI0_BASE + TWI_TNPR_OFF))
122 #define TWI0_TNCR (HWREG(TWI0_BASE + TWI_TNCR_OFF))
123 #define TWI0_PTCR (HWREG(TWI0_BASE + TWI_PTCR_OFF))
124 #define TWI0_PTSR (HWREG(TWI0_BASE + TWI_PTSR_OFF))
128 #define TWI1_CR (HWREG(TWI1_BASE + TWI_CR_OFF))
129 #define TWI1_MMR (HWREG(TWI1_BASE + TWI_MMR_OFF))
130 #define TWI1_SMR (HWREG(TWI1_BASE + TWI_SMR_OFF))
131 #define TWI1_IADR (HWREG(TWI1_BASE + TWI_IADR_OFF))
132 #define TWI1_CWGR (HWREG(TWI1_BASE + TWI_CWGR_OFF))
133 #define TWI1_SR (HWREG(TWI1_BASE + TWI_SR_OFF))
134 #define TWI1_IER (HWREG(TWI1_BASE + TWI_IER_OFF))
135 #define TWI1_IDR (HWREG(TWI1_BASE + TWI_IDR_OFF))
136 #define TWI1_IMR (HWREG(TWI1_BASE + TWI_IMR_OFF))
137 #define TWI1_RHR (HWREG(TWI1_BASE + TWI_RHR_OFF))
138 #define TWI1_THR (HWREG(TWI1_BASE + TWI_THR_OFF))
139 #define TWI1_RPR (HWREG(TWI1_BASE + TWI_RPR_OFF))
140 #define TWI1_RCR (HWREG(TWI1_BASE + TWI_RCR_OFF))
141 #define TWI1_TPR (HWREG(TWI1_BASE + TWI_TPR_OFF))
142 #define TWI1_TCR (HWREG(TWI1_BASE + TWI_TCR_OFF))
143 #define TWI1_RNPR (HWREG(TWI1_BASE + TWI_RNPR_OFF))
144 #define TWI1_RNCR (HWREG(TWI1_BASE + TWI_RNCR_OFF))
145 #define TWI1_TNPR (HWREG(TWI1_BASE + TWI_TNPR_OFF))
146 #define TWI1_TNCR (HWREG(TWI1_BASE + TWI_TNCR_OFF))
147 #define TWI1_PTCR (HWREG(TWI1_BASE + TWI_PTCR_OFF))
148 #define TWI1_PTSR (HWREG(TWI1_BASE + TWI_PTSR_OFF))
154 * TWI_CR: (TWI Offset: 0x00) Control Register
157 #define TWI_CR_START BV(0)
158 #define TWI_CR_STOP BV(1)
159 #define TWI_CR_MSEN BV(2)
160 #define TWI_CR_MSDIS BV(3)
161 #define TWI_CR_SVEN BV(4)
162 #define TWI_CR_SVDIS BV(5)
163 #define TWI_CR_QUICK BV(6)
164 #define TWI_CR_SWRST BV(7)
168 * TWI_MMR: (TWI Offset: 0x04) Master Mode Register
171 #define TWI_MMR_IADRSZ_SHIFT 8
172 #define TWI_MMR_IADRSZ_MASK (0x3 << TWI_MMR_IADRSZ_SHIFT)
173 #define TWI_MMR_IADRSZ_NONE (0x0 << 8)
174 #define TWI_MMR_IADRSZ_1_BYTE BV(8)
175 #define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8)
176 #define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8)
177 #define TWI_MMR_MREAD BV(12)
178 #define TWI_MMR_DADR_SHIFT 16
179 #define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
180 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_MASK & ((value) << TWI_MMR_DADR_SHIFT)))
184 * TWI_SMR: (TWI Offset: 0x08) Slave Mode Register
187 #define TWI_SMR_SADR_SHIFT 16
188 #define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT)
189 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_MASK & ((value) << TWI_SMR_SADR_SHIFT)))
193 * TWI_IADR: (TWI Offset: 0x0C) Internal Address Register
196 #define TWI_IADR_IADR_SHIFT 0
197 #define TWI_IADR_IADR_MASK (0xffffff << TWI_IADR_IADR_SHIFT)
198 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_MASK & ((value) << TWI_IADR_IADR_SHIFT)))
202 * TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register
205 #define TWI_CWGR_CLDIV_SHIFT 0
206 #define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
207 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_MASK & ((value) << TWI_CWGR_CLDIV_SHIFT)))
208 #define TWI_CWGR_CHDIV_SHIFT 8
209 #define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CHDIV_SHIFT)
210 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_MASK & ((value) << TWI_CWGR_CHDIV_SHIFT)))
211 #define TWI_CWGR_CKDIV_SHIFT 16
212 #define TWI_CWGR_CKDIV_MASK (0x7 << TWI_CWGR_CKDIV_SHIFT)
213 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_MASK & ((value) << TWI_CWGR_CKDIV_SHIFT)))
217 * TWI_SR: (TWI Offset: 0x20) Status Register
220 #define TWI_SR_TXCOMP BV(0)
221 #define TWI_SR_RXRDY BV(1)
222 #define TWI_SR_TXRDY BV(2)
223 #define TWI_SR_SVREAD BV(3)
224 #define TWI_SR_SVACC BV(4)
225 #define TWI_SR_GACC BV(5)
226 #define TWI_SR_OVRE BV(6)
227 #define TWI_SR_NACK BV(8)
228 #define TWI_SR_ARBLST BV(9)
229 #define TWI_SR_SCLWS BV(10)
230 #define TWI_SR_EOSACC BV(11)
231 #define TWI_SR_ENDRX BV(12)
232 #define TWI_SR_ENDTX BV(13)
233 #define TWI_SR_RXBUFF BV(14)
234 #define TWI_SR_TXBUFE BV(15)
238 * TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register
241 #define TWI_IER_TXCOMP BV(0)
242 #define TWI_IER_RXRDY BV(1)
243 #define TWI_IER_TXRDY BV(2)
244 #define TWI_IER_SVACC BV(4)
245 #define TWI_IER_GACC BV(5)
246 #define TWI_IER_OVRE BV(6)
247 #define TWI_IER_NACK BV(8)
248 #define TWI_IER_ARBLST BV(9)
249 #define TWI_IER_SCL_WS BV(10)
250 #define TWI_IER_EOSACC BV(11)
251 #define TWI_IER_ENDRX BV(12)
252 #define TWI_IER_ENDTX BV(13)
253 #define TWI_IER_RXBUFF BV(14)
254 #define TWI_IER_TXBUFE BV(15)
258 * TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register
261 #define TWI_IDR_TXCOMP BV(0)
262 #define TWI_IDR_RXRDY BV(1)
263 #define TWI_IDR_TXRDY BV(2)
264 #define TWI_IDR_SVACC BV(4)
265 #define TWI_IDR_GACC BV(5)
266 #define TWI_IDR_OVRE BV(6)
267 #define TWI_IDR_NACK BV(8)
268 #define TWI_IDR_ARBLST BV(9)
269 #define TWI_IDR_SCL_WS BV(10)
270 #define TWI_IDR_EOSACC BV(11)
271 #define TWI_IDR_ENDRX BV(12)
272 #define TWI_IDR_ENDTX BV(13)
273 #define TWI_IDR_RXBUFF BV(14)
274 #define TWI_IDR_TXBUFE BV(15)
278 * TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register
281 #define TWI_IMR_TXCOMP BV(0)
282 #define TWI_IMR_RXRDY BV(1)
283 #define TWI_IMR_TXRDY BV(2)
284 #define TWI_IMR_SVACC BV(4)
285 #define TWI_IMR_GACC BV(5)
286 #define TWI_IMR_OVRE BV(6)
287 #define TWI_IMR_NACK BV(8)
288 #define TWI_IMR_ARBLST BV(9)
289 #define TWI_IMR_SCL_WS BV(10)
290 #define TWI_IMR_EOSACC BV(11)
291 #define TWI_IMR_ENDRX BV(12)
292 #define TWI_IMR_ENDTX BV(13)
293 #define TWI_IMR_RXBUFF BV(14)
294 #define TWI_IMR_TXBUFE BV(15)
298 * TWI_RHR: (TWI Offset: 0x30) Receive Holding Register
301 #define TWI_RHR_RXDATA_SHIFT 0
302 #define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
306 * TWI_THR: (TWI Offset: 0x34) Transmit Holding Register
309 #define TWI_THR_TXDATA_SHIFT 0
310 #define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
311 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_MASK & ((value) << TWI_THR_TXDATA_SHIFT)))
315 * TWI_RPR: (TWI Offset: 0x100) Receive Pointer Register
318 #define TWI_RPR_RXPTR_SHIFT 0
319 #define TWI_RPR_RXPTR_MASK (0xffffffff << TWI_RPR_RXPTR_SHIFT)
320 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_MASK & ((value) << TWI_RPR_RXPTR_SHIFT)))
324 * TWI_RCR: (TWI Offset: 0x104) Receive Counter Register
327 #define TWI_RCR_RXCTR_SHIFT 0
328 #define TWI_RCR_RXCTR_MASK (0xffff << TWI_RCR_RXCTR_SHIFT)
329 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_MASK & ((value) << TWI_RCR_RXCTR_SHIFT)))
333 * TWI_TPR: (TWI Offset: 0x108) Transmit Pointer Register
336 #define TWI_TPR_TXPTR_SHIFT 0
337 #define TWI_TPR_TXPTR_MASK (0xffffffff << TWI_TPR_TXPTR_SHIFT)
338 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_MASK & ((value) << TWI_TPR_TXPTR_SHIFT)))
342 * TWI_TCR: (TWI Offset: 0x10C) Transmit Counter Register
345 #define TWI_TCR_TXCTR_SHIFT 0
346 #define TWI_TCR_TXCTR_MASK (0xffff << TWI_TCR_TXCTR_SHIFT)
347 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_MASK & ((value) << TWI_TCR_TXCTR_SHIFT)))
351 * TWI_RNPR: (TWI Offset: 0x110) Receive Next Pointer Register
354 #define TWI_RNPR_RXNPTR_SHIFT 0
355 #define TWI_RNPR_RXNPTR_MASK (0xffffffff << TWI_RNPR_RXNPTR_SHIFT)
356 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_MASK & ((value) << TWI_RNPR_RXNPTR_SHIFT)))
360 * TWI_RNCR: (TWI Offset: 0x114) Receive Next Counter Register
363 #define TWI_RNCR_RXNCTR_SHIFT 0
364 #define TWI_RNCR_RXNCTR_MASK (0xffff << TWI_RNCR_RXNCTR_SHIFT)
365 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_MASK & ((value) << TWI_RNCR_RXNCTR_SHIFT)))
369 * TWI_TNPR: (TWI Offset: 0x118) Transmit Next Pointer Register
372 #define TWI_TNPR_TXNPTR_SHIFT 0
373 #define TWI_TNPR_TXNPTR_MASK (0xffffffff << TWI_TNPR_TXNPTR_SHIFT)
374 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_MASK & ((value) << TWI_TNPR_TXNPTR_SHIFT)))
378 * TWI_TNCR: (TWI Offset: 0x11C) Transmit Next Counter Register
381 #define TWI_TNCR_TXNCTR_SHIFT 0
382 #define TWI_TNCR_TXNCTR_MASK (0xffff << TWI_TNCR_TXNCTR_SHIFT)
383 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_MASK & ((value) << TWI_TNCR_TXNCTR_SHIFT)))
387 * TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register
390 #define TWI_PTCR_RXTEN BV(0)
391 #define TWI_PTCR_RXTDIS BV(1)
392 #define TWI_PTCR_TXTEN BV(8)
393 #define TWI_PTCR_TXTDIS BV(9)
397 * TWI_PTSR: (TWI Offset: 0x124) Transfer Status Register
400 #define TWI_PTSR_RXTEN BV(0)
401 #define TWI_PTSR_TXTEN BV(8)
404 #endif /* SAM3_TWI_H */