4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief AT91SAM3 UART hardware.
40 * UART registers base addresses.
43 #define UART0_BASE 0x400E0600
44 #ifndef CPU_CM3_AT91SAM3U
45 #define UART1_BASE 0x400E0800
50 * UART register offsets.
53 #define UART_CR 0x000 //< Control Register
54 #define UART_MR 0x004 //< Mode Register
55 #define UART_IER 0x008 //< Interrupt Enable Register
56 #define UART_IDR 0x00C //< Interrupt Disable Register
57 #define UART_IMR 0x010 //< Interrupt Mask Register
58 #define UART_SR 0x014 //< Status Register
59 #define UART_RHR 0x018 //< Receive Holding Register
60 #define UART_THR 0x01C //< Transmit Holding Register
61 #define UART_BRGR 0x020 //< Baud Rate Generator Register
63 #define UART_RPR 0x100 //< Receive Pointer Register
64 #define UART_RCR 0x104 //< Receive Counter Register
65 #define UART_TPR 0x108 //< Transmit Pointer Register
66 #define UART_TCR 0x10C //< Transmit Counter Register
67 #define UART_RNPR 0x110 //< Receive Next Pointer Register
68 #define UART_RNCR 0x114 //< Receive Next Counter Register
69 #define UART_TNPR 0x118 //< Transmit Next Pointer Register
70 #define UART_TNCR 0x11C //< Transmit Next Counter Register
71 #define UART_PTCR 0x120 //< Transfer Control Register
72 #define UART_PTSR 0x124 //< Transfer Status Register
77 * Bit fields in the UART_CR register.
80 #define UART_CR_RSTRX BV(2) //< Reset Receiver
81 #define UART_CR_RSTTX BV(3) //< Reset Transmitter
82 #define UART_CR_RXEN BV(4) //< Receiver Enable
83 #define UART_CR_RXDIS BV(5) //< Receiver Disable
84 #define UART_CR_TXEN BV(6) //< Transmitter Enable
85 #define UART_CR_TXDIS BV(7) //< Transmitter Disable
86 #define UART_CR_RSTSTA BV(8) //< Reset Status Bits
90 * Bit fields in the UART_MR register.
93 #define UART_MR_PAR_S 9 //< Parity Type shift
94 #define UART_MR_PAR_M (0x7 << UART_MR_PAR_S) //< Parity Type mask
95 #define UART_MR_PAR_EVEN (0x0 << UART_MR_PAR_S) //< Even parity
96 #define UART_MR_PAR_ODD (0x1 << UART_MR_PAR_S) //< Odd parity
97 #define UART_MR_PAR_SPACE (0x2 << UART_MR_PAR_S) //< Space: parity forced to 0
98 #define UART_MR_PAR_MARK (0x3 << UART_MR_PAR_S) //< Mark: parity forced to 1
99 #define UART_MR_PAR_NO (0x4 << UART_MR_PAR_S) //< No parity
100 #define UART_MR_CHMODE_S 14 //< Channel Mode shift
101 #define UART_MR_CHMODE_M (0x3 << UART_MR_CHMODE_S) //< Channel Mode mask
102 #define UART_MR_CHMODE_NORMAL (0x0 << UART_MR_CHMODE_S) //< Normal Mode
103 #define UART_MR_CHMODE_AUTOMATIC (0x1 << UART_MR_CHMODE_S) //< Automatic Echo
104 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_S) //< Local Loopback
105 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_S) //< Remote Loopback
109 * Bit fields in the UART_IER register.
112 #define UART_IER_RXRDY BV(0) //< Enable RXRDY Interrupt
113 #define UART_IER_TXRDY BV(1) //< Enable TXRDY Interrupt
114 #define UART_IER_ENDRX BV(3) //< Enable End of Receive Transfer Interrupt
115 #define UART_IER_ENDTX BV(4) //< Enable End of Transmit Interrupt
116 #define UART_IER_OVRE BV(5) //< Enable Overrun Error Interrupt
117 #define UART_IER_FRAME BV(6) //< Enable Framing Error Interrupt
118 #define UART_IER_PARE BV(7) //< Enable Parity Error Interrupt
119 #define UART_IER_TXEMPTY BV(9) //< Enable TXEMPTY Interrupt
120 #define UART_IER_TXBUFE BV(11) //< Enable Buffer Empty Interrupt
121 #define UART_IER_RXBUFF BV(12) //< Enable Buffer Full Interrupt
125 * Bit fields in the UART_IDR register.
128 #define UART_IDR_RXRDY BV(0) //< Disable RXRDY Interrupt
129 #define UART_IDR_TXRDY BV(1) //< Disable TXRDY Interrupt
130 #define UART_IDR_ENDRX BV(3) //< Disable End of Receive Transfer Interrupt
131 #define UART_IDR_ENDTX BV(4) //< Disable End of Transmit Interrupt
132 #define UART_IDR_OVRE BV(5) //< Disable Overrun Error Interrupt
133 #define UART_IDR_FRAME BV(6) //< Disable Framing Error Interrupt
134 #define UART_IDR_PARE BV(7) //< Disable Parity Error Interrupt
135 #define UART_IDR_TXEMPTY BV(9) //< Disable TXEMPTY Interrupt
136 #define UART_IDR_TXBUFE BV(11) //< Disable Buffer Empty Interrupt
137 #define UART_IDR_RXBUFF BV(12) //< Disable Buffer Full Interrupt
141 * Bit fields in the UART_IMR register.
144 #define UART_IMR_RXRDY BV(0) //< Mask RXRDY Interrupt
145 #define UART_IMR_TXRDY BV(1) //< Disable TXRDY Interrupt
146 #define UART_IMR_ENDRX BV(3) //< Mask End of Receive Transfer Interrupt
147 #define UART_IMR_ENDTX BV(4) //< Mask End of Transmit Interrupt
148 #define UART_IMR_OVRE BV(5) //< Mask Overrun Error Interrupt
149 #define UART_IMR_FRAME BV(6) //< Mask Framing Error Interrupt
150 #define UART_IMR_PARE BV(7) //< Mask Parity Error Interrupt
151 #define UART_IMR_TXEMPTY BV(9) //< Mask TXEMPTY Interrupt
152 #define UART_IMR_TXBUFE BV(11) //< Mask TXBUFE Interrupt
153 #define UART_IMR_RXBUFF BV(12) //< Mask RXBUFF Interrupt
157 * Bit fields in the UART_SR register.
160 #define UART_SR_RXRDY BV(0) //< Receiver Ready
161 #define UART_SR_TXRDY BV(1) //< Transmitter Ready
162 #define UART_SR_ENDRX BV(3) //< End of Receiver Transfer
163 #define UART_SR_ENDTX BV(4) //< End of Transmitter Transfer
164 #define UART_SR_OVRE BV(5) //< Overrun Error
165 #define UART_SR_FRAME BV(6) //< Framing Error
166 #define UART_SR_PARE BV(7) //< Parity Error
167 #define UART_SR_TXEMPTY BV(9) //< Transmitter Empty
168 #define UART_SR_TXBUFE BV(11) //< Transmission Buffer Empty
169 #define UART_SR_RXBUFF BV(12) //< Receive Buffer Full
173 * Bit fields in the UART_RHR register.
176 #define UART_RHR_RXCHR_M 0xFF //< Received Character mask
177 #define UART_RHR_RXCHR_S 0 //< Received Character shift
181 * Bit fields in the UART_THR register.
184 #define UART_THR_TXCHR_M 0xFF //< Character to be Transmitted mask
185 #define UART_THR_TXCHR_S 0 //< Character to be Transmitted shift
189 * Bit fields in the UART_BRGR register.
192 #define UART_BRGR_CD_M 0xFFFF //< Clock Divisor mask
193 #define UART_BRGR_CD_S 0 //< Clock Divisor shift
197 * Bit fields in the UART_RPR register.
200 #define UART_RPR_RXPTR_M 0xFFFFFFFF //< Receive Pointer Register mask
201 #define UART_RPR_RXPTR_S 0 //< Receive Pointer Register shift
205 * Bit fields in the UART_RCR register.
208 #define UART_RCR_RXCTR_M 0xFFFF //< Receive Counter Register mask
209 #define UART_RCR_RXCTR_S 0 //< Receive Counter Register shift
213 * Bit fields in the UART_TPR register.
216 #define UART_TPR_TXPTR_M 0xFFFFFFFF //< Transmit Counter Register mask
217 #define UART_TPR_TXPTR_S 0 //< Transmit Counter Register shift
221 * Bit fields in the UART_TCR register.
224 #define UART_TCR_TXCTR_M 0xFFFF //< Transmit Counter Register mask
225 #define UART_TCR_TXCTR_S 0 //< Transmit Counter Register shift
229 * Bit fields in the UART_RNPR register.
232 #define UART_RNPR_RXNPTR_M 0xFFFFFFFF //< Receive Next Pointer mask
233 #define UART_RNPR_RXNPTR_S 0 //< Receive Next Pointer shift
237 * Bit fields in the UART_RNCR register.
240 #define UART_RNCR_RXNCTR_M 0xFFFF //< Receive Next Counter mask
241 #define UART_RNCR_RXNCTR_S 0 //< Receive Next Counter shift
245 * Bit fields in the UART_TNPR register.
248 #define UART_TNPR_TXNPTR_M 0xFFFFFFFF //< Transmit Next Pointer mask
249 #define UART_TNPR_TXNPTR_S 0 //< Transmit Next Pointer shift
253 * Bit fields in the UART_TNCR register.
256 #define UART_TNCR_TXNCTR_M 0xFFFF //< Transmit Counter Next mask
257 #define UART_TNCR_TXNCTR_S 0 //< Transmit Counter Next shift
261 * Bit fields in the UART_PTCR register.
264 #define UART_PTCR_RXTEN BV(0) //< Receiver Transfer Enable
265 #define UART_PTCR_RXTDIS BV(1) //< Receiver Transfer Disable
266 #define UART_PTCR_TXTEN BV(8) //< Transmitter Transfer Enable
267 #define UART_PTCR_TXTDIS BV(9) //< Transmitter Transfer Disable
271 * Bit fields in the UART_PTSR register.
274 #define UART_PTSR_RXTEN BV(0) //< Receiver Transfer Enable
275 #define UART_PTSR_TXTEN BV(8) //< Transmitter Transfer Enable
278 #endif /* SAM3_UART_H */