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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3 UART hardware.
40 * UART registers base addresses.
43 #define UART0_BASE 0x400E0600
45 #define UART1_BASE 0x400E0800
50 * UART register offsets.
53 #define UART_CR_OFF 0x000 //< Control Register
54 #define UART_MR_OFF 0x004 //< Mode Register
55 #define UART_IER_OFF 0x008 //< Interrupt Enable Register
56 #define UART_IDR_OFF 0x00C //< Interrupt Disable Register
57 #define UART_IMR_OFF 0x010 //< Interrupt Mask Register
58 #define UART_SR_OFF 0x014 //< Status Register
59 #define UART_RHR_OFF 0x018 //< Receive Holding Register
60 #define UART_THR_OFF 0x01C //< Transmit Holding Register
61 #define UART_BRGR_OFF 0x020 //< Baud Rate Generator Register
63 #define UART_RPR_OFF 0x100 //< Receive Pointer Register
64 #define UART_RCR_OFF 0x104 //< Receive Counter Register
65 #define UART_TPR_OFF 0x108 //< Transmit Pointer Register
66 #define UART_TCR_OFF 0x10C //< Transmit Counter Register
67 #define UART_RNPR_OFF 0x110 //< Receive Next Pointer Register
68 #define UART_RNCR_OFF 0x114 //< Receive Next Counter Register
69 #define UART_TNPR_OFF 0x118 //< Transmit Next Pointer Register
70 #define UART_TNCR_OFF 0x11C //< Transmit Next Counter Register
71 #define UART_PTCR_OFF 0x120 //< Transfer Control Register
72 #define UART_PTSR_OFF 0x124 //< Transfer Status Register
76 * UART register addresses.
79 #if defined(UART0_BASE)
80 #define UART0_ACCESS(offset) (*((reg32_t *)(UART0_BASE + (offset))))
82 #define UART_CR UART0_ACCESS(UART_CR_OFF) //< Control Register
83 #define UART_MR UART0_ACCESS(UART_MR_OFF) //< Mode Register
84 #define UART_IER UART0_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
85 #define UART_IDR UART0_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
86 #define UART_IMR UART0_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
87 #define UART_SR UART0_ACCESS(UART_SR_OFF) //< Status Register
88 #define UART_RHR UART0_ACCESS(UART_RHR_OFF) //< Receive Holding Register
89 #define UART_THR UART0_ACCESS(UART_THR_OFF) //< Transmit Holding Register
90 #define UART_BRGR UART0_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
92 #define UART_RPR UART0_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
93 #define UART_RCR UART0_ACCESS(UART_RCR_OFF) //< Receive Counter Register
94 #define UART_TPR UART0_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
95 #define UART_TCR UART0_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
96 #define UART_RNPR UART0_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
97 #define UART_RNCR UART0_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
98 #define UART_TNPR UART0_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
99 #define UART_TNCR UART0_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
100 #define UART_PTCR UART0_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
101 #define UART_PTSR UART0_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
102 #endif /* UART0_BASE */
104 #if defined(UART1_BASE)
105 #define UART1_ACCESS(offset) (*((reg32_t *)(UART1_BASE + (offset))))
107 #define UART_CR UART1_ACCESS(UART_CR_OFF) //< Control Register
108 #define UART_MR UART1_ACCESS(UART_MR_OFF) //< Mode Register
109 #define UART_IER UART1_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
110 #define UART_IDR UART1_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
111 #define UART_IMR UART1_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
112 #define UART_SR UART1_ACCESS(UART_SR_OFF) //< Status Register
113 #define UART_RHR UART1_ACCESS(UART_RHR_OFF) //< Receive Holding Register
114 #define UART_THR UART1_ACCESS(UART_THR_OFF) //< Transmit Holding Register
115 #define UART_BRGR UART1_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
117 #define UART_RPR UART1_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
118 #define UART_RCR UART1_ACCESS(UART_RCR_OFF) //< Receive Counter Register
119 #define UART_TPR UART1_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
120 #define UART_TCR UART1_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
121 #define UART_RNPR UART1_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
122 #define UART_RNCR UART1_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
123 #define UART_TNPR UART1_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
124 #define UART_TNCR UART1_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
125 #define UART_PTCR UART1_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
126 #define UART_PTSR UART1_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
127 #endif /* UART0_BASE */
131 * Bit fields in the UART_CR register.
134 #define UART_CR_RSTRX 2 //< Reset Receiver
135 #define UART_CR_RSTTX 3 //< Reset Transmitter
136 #define UART_CR_RXEN 4 //< Receiver Enable
137 #define UART_CR_RXDIS 5 //< Receiver Disable
138 #define UART_CR_TXEN 6 //< Transmitter Enable
139 #define UART_CR_TXDIS 7 //< Transmitter Disable
140 #define UART_CR_RSTSTA 8 //< Reset Status Bits
144 * Bit fields in the UART_MR register.
147 #define UART_MR_PAR_SHIFT 9 //< Parity Type shift
148 #define UART_MR_PAR_MASK (0x7 << UART_MR_PAR_SHIFT) //< Parity Type mask
149 #define UART_MR_PAR_EVEN (0x0 << UART_MR_PAR_SHIFT) //< Even parity
150 #define UART_MR_PAR_ODD (0x1 << UART_MR_PAR_SHIFT) //< Odd parity
151 #define UART_MR_PAR_SPACE (0x2 << UART_MR_PAR_SHIFT) //< Space: parity forced to 0
152 #define UART_MR_PAR_MARK (0x3 << UART_MR_PAR_SHIFT) //< Mark: parity forced to 1
153 #define UART_MR_PAR_NO (0x4 << UART_MR_PAR_SHIFT) //< No parity
154 #define UART_MR_CHMODE_SHIFT 14 //< Channel Mode shift
155 #define UART_MR_CHMODE_MASK (0x3 << UART_MR_CHMODE_SHIFT) //< Channel Mode mask
156 #define UART_MR_CHMODE_NORMAL (0x0 << UART_MR_CHMODE_SHIFT) //< Normal Mode
157 #define UART_MR_CHMODE_AUTOMATIC (0x1 << UART_MR_CHMODE_SHIFT) //< Automatic Echo
158 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SHIFT) //< Local Loopback
159 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SHIFT) //< Remote Loopback
163 * Bit fields in the UART_IER register.
166 #define UART_IER_RXRDY 0 //< Enable RXRDY Interrupt
167 #define UART_IER_TXRDY 1 //< Enable TXRDY Interrupt
168 #define UART_IER_ENDRX 3 //< Enable End of Receive Transfer Interrupt
169 #define UART_IER_ENDTX 4 //< Enable End of Transmit Interrupt
170 #define UART_IER_OVRE 5 //< Enable Overrun Error Interrupt
171 #define UART_IER_FRAME 6 //< Enable Framing Error Interrupt
172 #define UART_IER_PARE 7 //< Enable Parity Error Interrupt
173 #define UART_IER_TXEMPTY 9 //< Enable TXEMPTY Interrupt
174 #define UART_IER_TXBUFE 11 //< Enable Buffer Empty Interrupt
175 #define UART_IER_RXBUFF 12 //< Enable Buffer Full Interrupt
179 * Bit fields in the UART_IDR register.
182 #define UART_IDR_RXRDY 0 //< Disable RXRDY Interrupt
183 #define UART_IDR_TXRDY 1 //< Disable TXRDY Interrupt
184 #define UART_IDR_ENDRX 3 //< Disable End of Receive Transfer Interrupt
185 #define UART_IDR_ENDTX 4 //< Disable End of Transmit Interrupt
186 #define UART_IDR_OVRE 5 //< Disable Overrun Error Interrupt
187 #define UART_IDR_FRAME 6 //< Disable Framing Error Interrupt
188 #define UART_IDR_PARE 7 //< Disable Parity Error Interrupt
189 #define UART_IDR_TXEMPTY 9 //< Disable TXEMPTY Interrupt
190 #define UART_IDR_TXBUFE 11 //< Disable Buffer Empty Interrupt
191 #define UART_IDR_RXBUFF 12 //< Disable Buffer Full Interrupt
195 * Bit fields in the UART_IMR register.
198 #define UART_IMR_RXRDY 0 //< Mask RXRDY Interrupt
199 #define UART_IMR_TXRDY 1 //< Disable TXRDY Interrupt
200 #define UART_IMR_ENDRX 3 //< Mask End of Receive Transfer Interrupt
201 #define UART_IMR_ENDTX 4 //< Mask End of Transmit Interrupt
202 #define UART_IMR_OVRE 5 //< Mask Overrun Error Interrupt
203 #define UART_IMR_FRAME 6 //< Mask Framing Error Interrupt
204 #define UART_IMR_PARE 7 //< Mask Parity Error Interrupt
205 #define UART_IMR_TXEMPTY 9 //< Mask TXEMPTY Interrupt
206 #define UART_IMR_TXBUFE 11 //< Mask TXBUFE Interrupt
207 #define UART_IMR_RXBUFF 12 //< Mask RXBUFF Interrupt
211 * Bit fields in the UART_SR register.
214 #define UART_SR_RXRDY 0 //< Receiver Ready
215 #define UART_SR_TXRDY 1 //< Transmitter Ready
216 #define UART_SR_ENDRX 3 //< End of Receiver Transfer
217 #define UART_SR_ENDTX 4 //< End of Transmitter Transfer
218 #define UART_SR_OVRE 5 //< Overrun Error
219 #define UART_SR_FRAME 6 //< Framing Error
220 #define UART_SR_PARE 7 //< Parity Error
221 #define UART_SR_TXEMPTY 9 //< Transmitter Empty
222 #define UART_SR_TXBUFE 11 //< Transmission Buffer Empty
223 #define UART_SR_RXBUFF 12 //< Receive Buffer Full
227 * Bit fields in the UART_RHR register.
230 #define UART_RHR_RXCHR_MASK 0xFF //< Received Character mask
231 #define UART_RHR_RXCHR_SHIFT 0 //< Received Character shift
235 * Bit fields in the UART_THR register.
238 #define UART_THR_TXCHR_MASK 0xFF //< Character to be Transmitted mask
239 #define UART_THR_TXCHR_SHIFT 0 //< Character to be Transmitted shift
243 * Bit fields in the UART_BRGR register.
246 #define UART_BRGR_CD_MASK 0xFFFF //< Clock Divisor mask
247 #define UART_BRGR_CD_SHIFT 0 //< Clock Divisor shift
251 * Bit fields in the UART_RPR register.
254 #define UART_RPR_RXPTR_MASK 0xFFFFFFFF //< Receive Pointer Register mask
255 #define UART_RPR_RXPTR_SHIFT 0 //< Receive Pointer Register shift
259 * Bit fields in the UART_RCR register.
262 #define UART_RCR_RXCTR_MASK 0xFFFF //< Receive Counter Register mask
263 #define UART_RCR_RXCTR_SHIFT 0 //< Receive Counter Register shift
267 * Bit fields in the UART_TPR register.
270 #define UART_TPR_TXPTR_MASK 0xFFFFFFFF //< Transmit Counter Register mask
271 #define UART_TPR_TXPTR_SHIFT 0 //< Transmit Counter Register shift
275 * Bit fields in the UART_TCR register.
278 #define UART_TCR_TXCTR_MASK 0xFFFF //< Transmit Counter Register mask
279 #define UART_TCR_TXCTR_SHIFT 0 //< Transmit Counter Register shift
283 * Bit fields in the UART_RNPR register.
286 #define UART_RNPR_RXNPTR_MASK 0xFFFFFFFF //< Receive Next Pointer mask
287 #define UART_RNPR_RXNPTR_SHIFT 0 //< Receive Next Pointer shift
291 * Bit fields in the UART_RNCR register.
294 #define UART_RNCR_RXNCTR_MASK 0xFFFF //< Receive Next Counter mask
295 #define UART_RNCR_RXNCTR_SHIFT 0 //< Receive Next Counter shift
299 * Bit fields in the UART_TNPR register.
302 #define UART_TNPR_TXNPTR_MASK 0xFFFFFFFF //< Transmit Next Pointer mask
303 #define UART_TNPR_TXNPTR_SHIFT 0 //< Transmit Next Pointer shift
307 * Bit fields in the UART_TNCR register.
310 #define UART_TNCR_TXNCTR_MASK 0xFFFF //< Transmit Counter Next mask
311 #define UART_TNCR_TXNCTR_SHIFT 0 //< Transmit Counter Next shift
315 * Bit fields in the UART_PTCR register.
318 #define UART_PTCR_RXTEN 0 //< Receiver Transfer Enable
319 #define UART_PTCR_RXTDIS 1 //< Receiver Transfer Disable
320 #define UART_PTCR_TXTEN 8 //< Transmitter Transfer Enable
321 #define UART_PTCR_TXTDIS 9 //< Transmitter Transfer Disable
325 * Bit fields in the UART_PTSR register.
328 #define UART_PTSR_RXTEN 0 //< Receiver Transfer Enable
329 #define UART_PTSR_TXTEN 8 //< Transmitter Transfer Enable
332 #endif /* SAM3_UART_H */