4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \author Francesco Sacchi <batt@develer.com>
35 * Atmel SAM3 Watchdog.
36 * This file is based on NUT/OS implementation. See license below.
41 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of the copyright holders nor the names of
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
60 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
62 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
63 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
64 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
66 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * For additional information see http://www.ethernut.de/
75 /** Watch Dog registers base address */
76 #define WDT_BASE 0x400E1450
78 /** Watch Dog Control Register */
80 #define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset.
81 #define WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address.
82 #define WDT_WDRSTT 0 ///< Watchdog restart.
83 #define WDT_KEY 0xA5000000 ///< Watchdog password.
86 /** Watch Dog Mode Register */
88 #define WDT_MR_OFF 0x00000004 ///< Mode register offset.
89 #define WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address.
90 #define WDT_WDV_MASK 0x00000FFF ///< Counter value mask.
91 #define WDT_WDV_SHIFT 0 ///< Counter value LSB.
92 #define WDT_WDFIEN 12 ///< Fault interrupt enable.
93 #define WDT_WDRSTEN 13 ///< Reset enable.
94 #define WDT_WDRPROC 14 ///< Eset processor enable.
95 #define WDT_WDDIS 15 ///< Watchdog disable.
96 #define WDT_WDD_MASK 0x0FFF0000 ///< Delta value mask.
97 #define WDT_WDD_SHIFT 16 ///< Delta value LSB.
98 #define WDT_WDDBGHLT 28 ///< Watchdog debug halt.
99 #define WDT_WDIDLEHLT 29 ///< Watchdog idle halt.
102 /** Watch Dog Status Register */
104 #define WDT_SR_OFF 0x00000008 ///< Status register offset.
105 #define WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address.
106 #define WDT_WDUNF 0 ///< Watchdog underflow.
107 #define WDT_WDERR 1 ///< Watchdog error.
110 #endif /* SAM3_WDT_H */