4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 memory map.
36 #ifndef STM32_MEMMAP_H
37 #define STM32_MEMMAP_H
39 /* Peripheral and SRAM base address in the alias region */
40 #define PERIPH_BB_BASE (0x42000000)
41 #define SRAM_BB_BASE (0x22000000)
43 /* Peripheral and SRAM base address in the bit-band region */
44 #define SRAM_BASE (0x20000000)
45 #define PERIPH_BASE (0x40000000)
47 /* Flash refisters base address */
48 #define FLASH_BASE (0x40022000)
49 /* Flash Option Bytes base address */
50 #define OB_BASE (0x1FFFF800)
52 /* Peripheral memory map */
53 #define APB1PERIPH_BASE (PERIPH_BASE)
54 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
55 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
57 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
58 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
59 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
60 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
61 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
62 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
63 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
64 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
65 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
66 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
67 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
68 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
69 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
70 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
71 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
72 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
73 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
74 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
75 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
76 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
77 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
78 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
79 #define CEC_BASE (APB1PERIPH_BASE + 0x7800)
81 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
82 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
83 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
84 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
85 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
86 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
87 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
88 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
89 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
90 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
91 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
92 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
93 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
94 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
95 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
96 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
97 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
98 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
99 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
101 #define SDIO_BASE (PERIPH_BASE + 0x18000)
104 #define DMA1_BASE (AHBPERIPH_BASE + 0X0000)
105 #define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0008)
106 #define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0X001C)
107 #define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0030)
108 #define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0044)
109 #define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0058)
110 #define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0X006C)
111 #define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0X0080)
112 #define DMA2_BASE (AHBPERIPH_BASE + 0X0400)
113 #define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0408)
114 #define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0X041C)
115 #define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0430)
116 #define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0444)
117 #define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0458)
118 #define RCC_BASE (AHBPERIPH_BASE + 0X1000)
119 #define CRC_BASE (AHBPERIPH_BASE + 0X3000)
121 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) ///< Flash registers base address
123 #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
124 #define ETH_MAC_BASE (ETH_BASE)
125 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
126 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
127 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
129 #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) ///< FSMC Bank1 registers base address
130 #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) ///< FSMC Bank1E registers base address
131 #define FSMC_BANK2_R_BASE (FSMC_R_BASE + 0x0060) ///< FSMC Bank2 registers base address
132 #define FSMC_BANK3_R_BASE (FSMC_R_BASE + 0x0080) ///< FSMC Bank3 registers base address
133 #define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) ///< FSMC Bank4 registers base address
135 #define DBGMCU_BASE ((uint32_t)0xE0042000) ///< Debug MCU registers base address
137 /* System Control Space memory map */
138 #define SCS_BASE (0xE000E000)
140 #define SYSTICK_BASE (SCS_BASE + 0x0010)
141 #define NVIC_BASE (SCS_BASE + 0x0100)
142 #define SCB_BASE (SCS_BASE + 0x0D00)
144 #endif /* STM32_MEMMAP_H */