4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 memory map.
36 #ifndef STM32_MEMMAP_H
37 #define STM32_MEMMAP_H
39 /* Peripheral and SRAM base address in the alias region */
40 #define PERIPH_BB_BASE (0x42000000)
41 #define SRAM_BB_BASE (0x22000000)
43 /* Peripheral and SRAM base address in the bit-band region */
44 #define SRAM_BASE (0x20000000)
45 #define PERIPH_BASE (0x40000000)
47 /* Flash refisters base address */
48 #define FLASH_BASE (0x40022000)
49 /* Flash Option Bytes base address */
50 #define OB_BASE (0x1FFFF800)
52 /* Peripheral memory map */
53 #define APB1PERIPH_BASE (PERIPH_BASE)
54 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
55 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
57 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
58 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
59 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
60 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
61 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
62 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
63 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
64 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
65 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
66 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
67 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
68 #define CAN_BASE (APB1PERIPH_BASE + 0x6400)
69 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
70 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
72 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
73 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
74 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
75 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
76 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
77 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
78 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
79 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
80 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
81 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
82 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
83 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
85 #define DMA_BASE (AHBPERIPH_BASE + 0x0000)
86 #define DMA_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
87 #define DMA_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)
88 #define DMA_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030)
89 #define DMA_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044)
90 #define DMA_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058)
91 #define DMA_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C)
92 #define DMA_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080)
93 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
95 /* System Control Space memory map */
96 #define SCS_BASE (0xE000E000)
98 #define SYSTICK_BASE (SCS_BASE + 0x0010)
99 #define NVIC_BASE (SCS_BASE + 0x0100)
100 #define SCB_BASE (SCS_BASE + 0x0D00)
102 #endif /* STM32_MEMMAP_H */