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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief NVIC STM32F10xx registers definition.
41 * The following are defines for the fault assignments.
44 #define FAULT_NMI 2 ///< NMI fault
45 #define FAULT_HARD 3 ///< Hard fault
46 #define FAULT_MPU 4 ///< MPU fault
47 #define FAULT_BUS 5 ///< Bus fault
48 #define FAULT_USAGE 6 ///< Usage fault
49 #define FAULT_SVCALL 11 ///< SVCall
50 #define FAULT_DEBUG 12 ///< Debug monitor
51 #define FAULT_PENDSV 14 ///< PendSV
52 #define FAULT_SYSTICK 15 ///< System Tick
56 * NVIC registers (NVIC)
59 #define NVIC_INT_TYPE_R (*((reg32_t *)0xE000E004))
60 #define NVIC_ST_CTRL_R (*((reg32_t *)0xE000E010))
61 #define NVIC_ST_RELOAD_R (*((reg32_t *)0xE000E014))
62 #define NVIC_ST_CURRENT_R (*((reg32_t *)0xE000E018))
63 #define NVIC_ST_CAL_R (*((reg32_t *)0xE000E01C))
64 #define NVIC_EN0_R (*((reg32_t *)0xE000E100))
65 #define NVIC_EN1_R (*((reg32_t *)0xE000E104))
66 #define NVIC_DIS0_R (*((reg32_t *)0xE000E180))
67 #define NVIC_DIS1_R (*((reg32_t *)0xE000E184))
68 #define NVIC_PEND0_R (*((reg32_t *)0xE000E200))
69 #define NVIC_PEND1_R (*((reg32_t *)0xE000E204))
70 #define NVIC_UNPEND0_R (*((reg32_t *)0xE000E280))
71 #define NVIC_UNPEND1_R (*((reg32_t *)0xE000E284))
72 #define NVIC_ACTIVE0_R (*((reg32_t *)0xE000E300))
73 #define NVIC_ACTIVE1_R (*((reg32_t *)0xE000E304))
74 #define NVIC_PRI0_R (*((reg32_t *)0xE000E400))
75 #define NVIC_PRI1_R (*((reg32_t *)0xE000E404))
76 #define NVIC_PRI2_R (*((reg32_t *)0xE000E408))
77 #define NVIC_PRI3_R (*((reg32_t *)0xE000E40C))
78 #define NVIC_PRI4_R (*((reg32_t *)0xE000E410))
79 #define NVIC_PRI5_R (*((reg32_t *)0xE000E414))
80 #define NVIC_PRI6_R (*((reg32_t *)0xE000E418))
81 #define NVIC_PRI7_R (*((reg32_t *)0xE000E41C))
82 #define NVIC_PRI8_R (*((reg32_t *)0xE000E420))
83 #define NVIC_PRI9_R (*((reg32_t *)0xE000E424))
84 #define NVIC_PRI10_R (*((reg32_t *)0xE000E428))
85 #define NVIC_CPUID_R (*((reg32_t *)0xE000ED00))
86 #define NVIC_INT_CTRL_R (*((reg32_t *)0xE000ED04))
87 #define NVIC_VTABLE_R (*((reg32_t *)0xE000ED08))
88 #define NVIC_APINT_R (*((reg32_t *)0xE000ED0C))
89 #define NVIC_SYS_CTRL_R (*((reg32_t *)0xE000ED10))
90 #define NVIC_CFG_CTRL_R (*((reg32_t *)0xE000ED14))
91 #define NVIC_SYS_PRI1_R (*((reg32_t *)0xE000ED18))
92 #define NVIC_SYS_PRI2_R (*((reg32_t *)0xE000ED1C))
93 #define NVIC_SYS_PRI3_R (*((reg32_t *)0xE000ED20))
94 #define NVIC_SYS_HND_CTRL_R (*((reg32_t *)0xE000ED24))
95 #define NVIC_FAULT_STAT_R (*((reg32_t *)0xE000ED28))
96 #define NVIC_HFAULT_STAT_R (*((reg32_t *)0xE000ED2C))
97 #define NVIC_DEBUG_STAT_R (*((reg32_t *)0xE000ED30))
98 #define NVIC_MM_ADDR_R (*((reg32_t *)0xE000ED34))
99 #define NVIC_FAULT_ADDR_R (*((reg32_t *)0xE000ED38))
100 #define NVIC_MPU_TYPE_R (*((reg32_t *)0xE000ED90))
101 #define NVIC_MPU_CTRL_R (*((reg32_t *)0xE000ED94))
102 #define NVIC_MPU_NUMBER_R (*((reg32_t *)0xE000ED98))
103 #define NVIC_MPU_BASE_R (*((reg32_t *)0xE000ED9C))
104 #define NVIC_MPU_ATTR_R (*((reg32_t *)0xE000EDA0))
105 #define NVIC_DBG_CTRL_R (*((reg32_t *)0xE000EDF0))
106 #define NVIC_DBG_XFER_R (*((reg32_t *)0xE000EDF4))
107 #define NVIC_DBG_DATA_R (*((reg32_t *)0xE000EDF8))
108 #define NVIC_DBG_INT_R (*((reg32_t *)0xE000EDFC))
109 #define NVIC_SW_TRIG_R (*((reg32_t *)0xE000EF00))
113 * The following are defines for the NVIC register addresses.
116 #define NVIC_INT_TYPE 0xE000E004 ///< Interrupt Controller Type Reg
117 #define NVIC_ST_CTRL 0xE000E010 ///< SysTick Control and Status Reg
118 #define NVIC_ST_RELOAD 0xE000E014 ///< SysTick Reload Value Register
119 #define NVIC_ST_CURRENT 0xE000E018 ///< SysTick Current Value Register
120 #define NVIC_ST_CAL 0xE000E01C ///< SysTick Calibration Value Reg
121 #define NVIC_EN0 0xE000E100 ///< IRQ 0 to 31 Set Enable Register
122 #define NVIC_EN1 0xE000E104 ///< IRQ 32 to 63 Set Enable Register
123 #define NVIC_DIS0 0xE000E180 ///< IRQ 0 to 31 Clear Enable Reg
124 #define NVIC_DIS1 0xE000E184 ///< IRQ 32 to 63 Clear Enable Reg
125 #define NVIC_PEND0 0xE000E200 ///< IRQ 0 to 31 Set Pending Register
126 #define NVIC_PEND1 0xE000E204 ///< IRQ 32 to 63 Set Pending Reg
127 #define NVIC_UNPEND0 0xE000E280 ///< IRQ 0 to 31 Clear Pending Reg
128 #define NVIC_UNPEND1 0xE000E284 ///< IRQ 32 to 63 Clear Pending Reg
129 #define NVIC_ACTIVE0 0xE000E300 ///< IRQ 0 to 31 Active Register
130 #define NVIC_ACTIVE1 0xE000E304 ///< IRQ 32 to 63 Active Register
131 #define NVIC_PRI0 0xE000E400 ///< IRQ 0 to 3 Priority Register
132 #define NVIC_PRI1 0xE000E404 ///< IRQ 4 to 7 Priority Register
133 #define NVIC_PRI2 0xE000E408 ///< IRQ 8 to 11 Priority Register
134 #define NVIC_PRI3 0xE000E40C ///< IRQ 12 to 15 Priority Register
135 #define NVIC_PRI4 0xE000E410 ///< IRQ 16 to 19 Priority Register
136 #define NVIC_PRI5 0xE000E414 ///< IRQ 20 to 23 Priority Register
137 #define NVIC_PRI6 0xE000E418 ///< IRQ 24 to 27 Priority Register
138 #define NVIC_PRI7 0xE000E41C ///< IRQ 28 to 31 Priority Register
139 #define NVIC_PRI8 0xE000E420 ///< IRQ 32 to 35 Priority Register
140 #define NVIC_PRI9 0xE000E424 ///< IRQ 36 to 39 Priority Register
141 #define NVIC_PRI10 0xE000E428 ///< IRQ 40 to 43 Priority Register
142 #define NVIC_PRI11 0xE000E42C ///< IRQ 44 to 47 Priority Register
143 #define NVIC_PRI12 0xE000E430 ///< IRQ 48 to 51 Priority Register
144 #define NVIC_PRI13 0xE000E434 ///< IRQ 52 to 55 Priority Register
145 #define NVIC_CPUID 0xE000ED00 ///< CPUID Base Register
146 #define NVIC_INT_CTRL 0xE000ED04 ///< Interrupt Control State Register
147 #define NVIC_VTABLE 0xE000ED08 ///< Vector Table Offset Register
148 #define NVIC_APINT 0xE000ED0C ///< App. Int & Reset Control Reg
149 #define NVIC_SYS_CTRL 0xE000ED10 ///< System Control Register
150 #define NVIC_CFG_CTRL 0xE000ED14 ///< Configuration Control Register
151 #define NVIC_SYS_PRI1 0xE000ED18 ///< Sys. Handlers 4 to 7 Priority
152 #define NVIC_SYS_PRI2 0xE000ED1C ///< Sys. Handlers 8 to 11 Priority
153 #define NVIC_SYS_PRI3 0xE000ED20 ///< Sys. Handlers 12 to 15 Priority
154 #define NVIC_SYS_HND_CTRL 0xE000ED24 ///< System Handler Control and State
155 #define NVIC_FAULT_STAT 0xE000ED28 ///< Configurable Fault Status Reg
156 #define NVIC_HFAULT_STAT 0xE000ED2C ///< Hard Fault Status Register
157 #define NVIC_DEBUG_STAT 0xE000ED30 ///< Debug Status Register
158 #define NVIC_MM_ADDR 0xE000ED34 ///< Mem Manage Address Register
159 #define NVIC_FAULT_ADDR 0xE000ED38 ///< Bus Fault Address Register
160 #define NVIC_MPU_TYPE 0xE000ED90 ///< MPU Type Register
161 #define NVIC_MPU_CTRL 0xE000ED94 ///< MPU Control Register
162 #define NVIC_MPU_NUMBER 0xE000ED98 ///< MPU Region Number Register
163 #define NVIC_MPU_BASE 0xE000ED9C ///< MPU Region Base Address Register
164 #define NVIC_MPU_ATTR 0xE000EDA0 ///< MPU Region Attribute & Size Reg
165 #define NVIC_DBG_CTRL 0xE000EDF0 ///< Debug Control and Status Reg
166 #define NVIC_DBG_XFER 0xE000EDF4 ///< Debug Core Reg. Transfer Select
167 #define NVIC_DBG_DATA 0xE000EDF8 ///< Debug Core Register Data
168 #define NVIC_DBG_INT 0xE000EDFC ///< Debug Reset Interrupt Control
169 #define NVIC_SW_TRIG 0xE000EF00 ///< Software Trigger Interrupt Reg
173 * The following are defines for the bit fields in the NVIC_INT_TYPE register.
176 #define NVIC_INT_TYPE_LINES_M 0x0000001F ///< Number of interrupt lines (x32)
177 #define NVIC_INT_TYPE_LINES_S 0
181 * The following are defines for the bit fields in the NVIC_ST_CTRL register.
184 #define NVIC_ST_CTRL_COUNT 0x00010000 ///< Count flag
185 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 ///< Clock Source
186 #define NVIC_ST_CTRL_INTEN 0x00000002 ///< Interrupt enable
187 #define NVIC_ST_CTRL_ENABLE 0x00000001 ///< Counter mode
191 * The following are defines for the bit fields in the NVIC_ST_RELOAD register.
194 #define NVIC_ST_RELOAD_M 0x00FFFFFF ///< Counter load value
195 #define NVIC_ST_RELOAD_S 0
199 * The following are defines for the bit fields in the NVIC_ST_CURRENT
203 #define NVIC_ST_CURRENT_M 0x00FFFFFF ///< Counter current value
204 #define NVIC_ST_CURRENT_S 0
208 * The following are defines for the bit fields in the NVIC_ST_CAL register.
211 #define NVIC_ST_CAL_NOREF 0x80000000 ///< No reference clock
212 #define NVIC_ST_CAL_SKEW 0x40000000 ///< Clock skew
213 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF ///< 1ms reference value
214 #define NVIC_ST_CAL_ONEMS_S 0
218 * The following are defines for the bit fields in the NVIC_EN0 register.
221 #define NVIC_EN0_INT31 0x80000000 ///< Interrupt 31 enable
222 #define NVIC_EN0_INT30 0x40000000 ///< Interrupt 30 enable
223 #define NVIC_EN0_INT29 0x20000000 ///< Interrupt 29 enable
224 #define NVIC_EN0_INT28 0x10000000 ///< Interrupt 28 enable
225 #define NVIC_EN0_INT27 0x08000000 ///< Interrupt 27 enable
226 #define NVIC_EN0_INT26 0x04000000 ///< Interrupt 26 enable
227 #define NVIC_EN0_INT25 0x02000000 ///< Interrupt 25 enable
228 #define NVIC_EN0_INT24 0x01000000 ///< Interrupt 24 enable
229 #define NVIC_EN0_INT23 0x00800000 ///< Interrupt 23 enable
230 #define NVIC_EN0_INT22 0x00400000 ///< Interrupt 22 enable
231 #define NVIC_EN0_INT21 0x00200000 ///< Interrupt 21 enable
232 #define NVIC_EN0_INT20 0x00100000 ///< Interrupt 20 enable
233 #define NVIC_EN0_INT19 0x00080000 ///< Interrupt 19 enable
234 #define NVIC_EN0_INT18 0x00040000 ///< Interrupt 18 enable
235 #define NVIC_EN0_INT17 0x00020000 ///< Interrupt 17 enable
236 #define NVIC_EN0_INT16 0x00010000 ///< Interrupt 16 enable
237 #define NVIC_EN0_INT15 0x00008000 ///< Interrupt 15 enable
238 #define NVIC_EN0_INT14 0x00004000 ///< Interrupt 14 enable
239 #define NVIC_EN0_INT13 0x00002000 ///< Interrupt 13 enable
240 #define NVIC_EN0_INT12 0x00001000 ///< Interrupt 12 enable
241 #define NVIC_EN0_INT11 0x00000800 ///< Interrupt 11 enable
242 #define NVIC_EN0_INT10 0x00000400 ///< Interrupt 10 enable
243 #define NVIC_EN0_INT9 0x00000200 ///< Interrupt 9 enable
244 #define NVIC_EN0_INT8 0x00000100 ///< Interrupt 8 enable
245 #define NVIC_EN0_INT7 0x00000080 ///< Interrupt 7 enable
246 #define NVIC_EN0_INT6 0x00000040 ///< Interrupt 6 enable
247 #define NVIC_EN0_INT5 0x00000020 ///< Interrupt 5 enable
248 #define NVIC_EN0_INT4 0x00000010 ///< Interrupt 4 enable
249 #define NVIC_EN0_INT3 0x00000008 ///< Interrupt 3 enable
250 #define NVIC_EN0_INT2 0x00000004 ///< Interrupt 2 enable
251 #define NVIC_EN0_INT1 0x00000002 ///< Interrupt 1 enable
252 #define NVIC_EN0_INT0 0x00000001 ///< Interrupt 0 enable
256 * The following are defines for the bit fields in the NVIC_EN1 register.
259 #define NVIC_EN1_INT59 0x08000000 ///< Interrupt 59 enable
260 #define NVIC_EN1_INT58 0x04000000 ///< Interrupt 58 enable
261 #define NVIC_EN1_INT57 0x02000000 ///< Interrupt 57 enable
262 #define NVIC_EN1_INT56 0x01000000 ///< Interrupt 56 enable
263 #define NVIC_EN1_INT55 0x00800000 ///< Interrupt 55 enable
264 #define NVIC_EN1_INT54 0x00400000 ///< Interrupt 54 enable
265 #define NVIC_EN1_INT53 0x00200000 ///< Interrupt 53 enable
266 #define NVIC_EN1_INT52 0x00100000 ///< Interrupt 52 enable
267 #define NVIC_EN1_INT51 0x00080000 ///< Interrupt 51 enable
268 #define NVIC_EN1_INT50 0x00040000 ///< Interrupt 50 enable
269 #define NVIC_EN1_INT49 0x00020000 ///< Interrupt 49 enable
270 #define NVIC_EN1_INT48 0x00010000 ///< Interrupt 48 enable
271 #define NVIC_EN1_INT47 0x00008000 ///< Interrupt 47 enable
272 #define NVIC_EN1_INT46 0x00004000 ///< Interrupt 46 enable
273 #define NVIC_EN1_INT45 0x00002000 ///< Interrupt 45 enable
274 #define NVIC_EN1_INT44 0x00001000 ///< Interrupt 44 enable
275 #define NVIC_EN1_INT43 0x00000800 ///< Interrupt 43 enable
276 #define NVIC_EN1_INT42 0x00000400 ///< Interrupt 42 enable
277 #define NVIC_EN1_INT41 0x00000200 ///< Interrupt 41 enable
278 #define NVIC_EN1_INT40 0x00000100 ///< Interrupt 40 enable
279 #define NVIC_EN1_INT39 0x00000080 ///< Interrupt 39 enable
280 #define NVIC_EN1_INT38 0x00000040 ///< Interrupt 38 enable
281 #define NVIC_EN1_INT37 0x00000020 ///< Interrupt 37 enable
282 #define NVIC_EN1_INT36 0x00000010 ///< Interrupt 36 enable
283 #define NVIC_EN1_INT35 0x00000008 ///< Interrupt 35 enable
284 #define NVIC_EN1_INT34 0x00000004 ///< Interrupt 34 enable
285 #define NVIC_EN1_INT33 0x00000002 ///< Interrupt 33 enable
286 #define NVIC_EN1_INT32 0x00000001 ///< Interrupt 32 enable
290 * The following are defines for the bit fields in the NVIC_DIS0 register.
293 #define NVIC_DIS0_INT31 0x80000000 ///< Interrupt 31 disable
294 #define NVIC_DIS0_INT30 0x40000000 ///< Interrupt 30 disable
295 #define NVIC_DIS0_INT29 0x20000000 ///< Interrupt 29 disable
296 #define NVIC_DIS0_INT28 0x10000000 ///< Interrupt 28 disable
297 #define NVIC_DIS0_INT27 0x08000000 ///< Interrupt 27 disable
298 #define NVIC_DIS0_INT26 0x04000000 ///< Interrupt 26 disable
299 #define NVIC_DIS0_INT25 0x02000000 ///< Interrupt 25 disable
300 #define NVIC_DIS0_INT24 0x01000000 ///< Interrupt 24 disable
301 #define NVIC_DIS0_INT23 0x00800000 ///< Interrupt 23 disable
302 #define NVIC_DIS0_INT22 0x00400000 ///< Interrupt 22 disable
303 #define NVIC_DIS0_INT21 0x00200000 ///< Interrupt 21 disable
304 #define NVIC_DIS0_INT20 0x00100000 ///< Interrupt 20 disable
305 #define NVIC_DIS0_INT19 0x00080000 ///< Interrupt 19 disable
306 #define NVIC_DIS0_INT18 0x00040000 ///< Interrupt 18 disable
307 #define NVIC_DIS0_INT17 0x00020000 ///< Interrupt 17 disable
308 #define NVIC_DIS0_INT16 0x00010000 ///< Interrupt 16 disable
309 #define NVIC_DIS0_INT15 0x00008000 ///< Interrupt 15 disable
310 #define NVIC_DIS0_INT14 0x00004000 ///< Interrupt 14 disable
311 #define NVIC_DIS0_INT13 0x00002000 ///< Interrupt 13 disable
312 #define NVIC_DIS0_INT12 0x00001000 ///< Interrupt 12 disable
313 #define NVIC_DIS0_INT11 0x00000800 ///< Interrupt 11 disable
314 #define NVIC_DIS0_INT10 0x00000400 ///< Interrupt 10 disable
315 #define NVIC_DIS0_INT9 0x00000200 ///< Interrupt 9 disable
316 #define NVIC_DIS0_INT8 0x00000100 ///< Interrupt 8 disable
317 #define NVIC_DIS0_INT7 0x00000080 ///< Interrupt 7 disable
318 #define NVIC_DIS0_INT6 0x00000040 ///< Interrupt 6 disable
319 #define NVIC_DIS0_INT5 0x00000020 ///< Interrupt 5 disable
320 #define NVIC_DIS0_INT4 0x00000010 ///< Interrupt 4 disable
321 #define NVIC_DIS0_INT3 0x00000008 ///< Interrupt 3 disable
322 #define NVIC_DIS0_INT2 0x00000004 ///< Interrupt 2 disable
323 #define NVIC_DIS0_INT1 0x00000002 ///< Interrupt 1 disable
324 #define NVIC_DIS0_INT0 0x00000001 ///< Interrupt 0 disable
328 * The following are defines for the bit fields in the NVIC_DIS1 register.
331 #define NVIC_DIS1_INT59 0x08000000 ///< Interrupt 59 disable
332 #define NVIC_DIS1_INT58 0x04000000 ///< Interrupt 58 disable
333 #define NVIC_DIS1_INT57 0x02000000 ///< Interrupt 57 disable
334 #define NVIC_DIS1_INT56 0x01000000 ///< Interrupt 56 disable
335 #define NVIC_DIS1_INT55 0x00800000 ///< Interrupt 55 disable
336 #define NVIC_DIS1_INT54 0x00400000 ///< Interrupt 54 disable
337 #define NVIC_DIS1_INT53 0x00200000 ///< Interrupt 53 disable
338 #define NVIC_DIS1_INT52 0x00100000 ///< Interrupt 52 disable
339 #define NVIC_DIS1_INT51 0x00080000 ///< Interrupt 51 disable
340 #define NVIC_DIS1_INT50 0x00040000 ///< Interrupt 50 disable
341 #define NVIC_DIS1_INT49 0x00020000 ///< Interrupt 49 disable
342 #define NVIC_DIS1_INT48 0x00010000 ///< Interrupt 48 disable
343 #define NVIC_DIS1_INT47 0x00008000 ///< Interrupt 47 disable
344 #define NVIC_DIS1_INT46 0x00004000 ///< Interrupt 46 disable
345 #define NVIC_DIS1_INT45 0x00002000 ///< Interrupt 45 disable
346 #define NVIC_DIS1_INT44 0x00001000 ///< Interrupt 44 disable
347 #define NVIC_DIS1_INT43 0x00000800 ///< Interrupt 43 disable
348 #define NVIC_DIS1_INT42 0x00000400 ///< Interrupt 42 disable
349 #define NVIC_DIS1_INT41 0x00000200 ///< Interrupt 41 disable
350 #define NVIC_DIS1_INT40 0x00000100 ///< Interrupt 40 disable
351 #define NVIC_DIS1_INT39 0x00000080 ///< Interrupt 39 disable
352 #define NVIC_DIS1_INT38 0x00000040 ///< Interrupt 38 disable
353 #define NVIC_DIS1_INT37 0x00000020 ///< Interrupt 37 disable
354 #define NVIC_DIS1_INT36 0x00000010 ///< Interrupt 36 disable
355 #define NVIC_DIS1_INT35 0x00000008 ///< Interrupt 35 disable
356 #define NVIC_DIS1_INT34 0x00000004 ///< Interrupt 34 disable
357 #define NVIC_DIS1_INT33 0x00000002 ///< Interrupt 33 disable
358 #define NVIC_DIS1_INT32 0x00000001 ///< Interrupt 32 disable
362 * The following are defines for the bit fields in the NVIC_PEND0 register.
365 #define NVIC_PEND0_INT31 0x80000000 ///< Interrupt 31 pend
366 #define NVIC_PEND0_INT30 0x40000000 ///< Interrupt 30 pend
367 #define NVIC_PEND0_INT29 0x20000000 ///< Interrupt 29 pend
368 #define NVIC_PEND0_INT28 0x10000000 ///< Interrupt 28 pend
369 #define NVIC_PEND0_INT27 0x08000000 ///< Interrupt 27 pend
370 #define NVIC_PEND0_INT26 0x04000000 ///< Interrupt 26 pend
371 #define NVIC_PEND0_INT25 0x02000000 ///< Interrupt 25 pend
372 #define NVIC_PEND0_INT24 0x01000000 ///< Interrupt 24 pend
373 #define NVIC_PEND0_INT23 0x00800000 ///< Interrupt 23 pend
374 #define NVIC_PEND0_INT22 0x00400000 ///< Interrupt 22 pend
375 #define NVIC_PEND0_INT21 0x00200000 ///< Interrupt 21 pend
376 #define NVIC_PEND0_INT20 0x00100000 ///< Interrupt 20 pend
377 #define NVIC_PEND0_INT19 0x00080000 ///< Interrupt 19 pend
378 #define NVIC_PEND0_INT18 0x00040000 ///< Interrupt 18 pend
379 #define NVIC_PEND0_INT17 0x00020000 ///< Interrupt 17 pend
380 #define NVIC_PEND0_INT16 0x00010000 ///< Interrupt 16 pend
381 #define NVIC_PEND0_INT15 0x00008000 ///< Interrupt 15 pend
382 #define NVIC_PEND0_INT14 0x00004000 ///< Interrupt 14 pend
383 #define NVIC_PEND0_INT13 0x00002000 ///< Interrupt 13 pend
384 #define NVIC_PEND0_INT12 0x00001000 ///< Interrupt 12 pend
385 #define NVIC_PEND0_INT11 0x00000800 ///< Interrupt 11 pend
386 #define NVIC_PEND0_INT10 0x00000400 ///< Interrupt 10 pend
387 #define NVIC_PEND0_INT9 0x00000200 ///< Interrupt 9 pend
388 #define NVIC_PEND0_INT8 0x00000100 ///< Interrupt 8 pend
389 #define NVIC_PEND0_INT7 0x00000080 ///< Interrupt 7 pend
390 #define NVIC_PEND0_INT6 0x00000040 ///< Interrupt 6 pend
391 #define NVIC_PEND0_INT5 0x00000020 ///< Interrupt 5 pend
392 #define NVIC_PEND0_INT4 0x00000010 ///< Interrupt 4 pend
393 #define NVIC_PEND0_INT3 0x00000008 ///< Interrupt 3 pend
394 #define NVIC_PEND0_INT2 0x00000004 ///< Interrupt 2 pend
395 #define NVIC_PEND0_INT1 0x00000002 ///< Interrupt 1 pend
396 #define NVIC_PEND0_INT0 0x00000001 ///< Interrupt 0 pend
400 * The following are defines for the bit fields in the NVIC_PEND1 register.
403 #define NVIC_PEND1_INT59 0x08000000 ///< Interrupt 59 pend
404 #define NVIC_PEND1_INT58 0x04000000 ///< Interrupt 58 pend
405 #define NVIC_PEND1_INT57 0x02000000 ///< Interrupt 57 pend
406 #define NVIC_PEND1_INT56 0x01000000 ///< Interrupt 56 pend
407 #define NVIC_PEND1_INT55 0x00800000 ///< Interrupt 55 pend
408 #define NVIC_PEND1_INT54 0x00400000 ///< Interrupt 54 pend
409 #define NVIC_PEND1_INT53 0x00200000 ///< Interrupt 53 pend
410 #define NVIC_PEND1_INT52 0x00100000 ///< Interrupt 52 pend
411 #define NVIC_PEND1_INT51 0x00080000 ///< Interrupt 51 pend
412 #define NVIC_PEND1_INT50 0x00040000 ///< Interrupt 50 pend
413 #define NVIC_PEND1_INT49 0x00020000 ///< Interrupt 49 pend
414 #define NVIC_PEND1_INT48 0x00010000 ///< Interrupt 48 pend
415 #define NVIC_PEND1_INT47 0x00008000 ///< Interrupt 47 pend
416 #define NVIC_PEND1_INT46 0x00004000 ///< Interrupt 46 pend
417 #define NVIC_PEND1_INT45 0x00002000 ///< Interrupt 45 pend
418 #define NVIC_PEND1_INT44 0x00001000 ///< Interrupt 44 pend
419 #define NVIC_PEND1_INT43 0x00000800 ///< Interrupt 43 pend
420 #define NVIC_PEND1_INT42 0x00000400 ///< Interrupt 42 pend
421 #define NVIC_PEND1_INT41 0x00000200 ///< Interrupt 41 pend
422 #define NVIC_PEND1_INT40 0x00000100 ///< Interrupt 40 pend
423 #define NVIC_PEND1_INT39 0x00000080 ///< Interrupt 39 pend
424 #define NVIC_PEND1_INT38 0x00000040 ///< Interrupt 38 pend
425 #define NVIC_PEND1_INT37 0x00000020 ///< Interrupt 37 pend
426 #define NVIC_PEND1_INT36 0x00000010 ///< Interrupt 36 pend
427 #define NVIC_PEND1_INT35 0x00000008 ///< Interrupt 35 pend
428 #define NVIC_PEND1_INT34 0x00000004 ///< Interrupt 34 pend
429 #define NVIC_PEND1_INT33 0x00000002 ///< Interrupt 33 pend
430 #define NVIC_PEND1_INT32 0x00000001 ///< Interrupt 32 pend
434 * The following are defines for the bit fields in the NVIC_UNPEND0 register.
437 #define NVIC_UNPEND0_INT31 0x80000000 ///< Interrupt 31 unpend
438 #define NVIC_UNPEND0_INT30 0x40000000 ///< Interrupt 30 unpend
439 #define NVIC_UNPEND0_INT29 0x20000000 ///< Interrupt 29 unpend
440 #define NVIC_UNPEND0_INT28 0x10000000 ///< Interrupt 28 unpend
441 #define NVIC_UNPEND0_INT27 0x08000000 ///< Interrupt 27 unpend
442 #define NVIC_UNPEND0_INT26 0x04000000 ///< Interrupt 26 unpend
443 #define NVIC_UNPEND0_INT25 0x02000000 ///< Interrupt 25 unpend
444 #define NVIC_UNPEND0_INT24 0x01000000 ///< Interrupt 24 unpend
445 #define NVIC_UNPEND0_INT23 0x00800000 ///< Interrupt 23 unpend
446 #define NVIC_UNPEND0_INT22 0x00400000 ///< Interrupt 22 unpend
447 #define NVIC_UNPEND0_INT21 0x00200000 ///< Interrupt 21 unpend
448 #define NVIC_UNPEND0_INT20 0x00100000 ///< Interrupt 20 unpend
449 #define NVIC_UNPEND0_INT19 0x00080000 ///< Interrupt 19 unpend
450 #define NVIC_UNPEND0_INT18 0x00040000 ///< Interrupt 18 unpend
451 #define NVIC_UNPEND0_INT17 0x00020000 ///< Interrupt 17 unpend
452 #define NVIC_UNPEND0_INT16 0x00010000 ///< Interrupt 16 unpend
453 #define NVIC_UNPEND0_INT15 0x00008000 ///< Interrupt 15 unpend
454 #define NVIC_UNPEND0_INT14 0x00004000 ///< Interrupt 14 unpend
455 #define NVIC_UNPEND0_INT13 0x00002000 ///< Interrupt 13 unpend
456 #define NVIC_UNPEND0_INT12 0x00001000 ///< Interrupt 12 unpend
457 #define NVIC_UNPEND0_INT11 0x00000800 ///< Interrupt 11 unpend
458 #define NVIC_UNPEND0_INT10 0x00000400 ///< Interrupt 10 unpend
459 #define NVIC_UNPEND0_INT9 0x00000200 ///< Interrupt 9 unpend
460 #define NVIC_UNPEND0_INT8 0x00000100 ///< Interrupt 8 unpend
461 #define NVIC_UNPEND0_INT7 0x00000080 ///< Interrupt 7 unpend
462 #define NVIC_UNPEND0_INT6 0x00000040 ///< Interrupt 6 unpend
463 #define NVIC_UNPEND0_INT5 0x00000020 ///< Interrupt 5 unpend
464 #define NVIC_UNPEND0_INT4 0x00000010 ///< Interrupt 4 unpend
465 #define NVIC_UNPEND0_INT3 0x00000008 ///< Interrupt 3 unpend
466 #define NVIC_UNPEND0_INT2 0x00000004 ///< Interrupt 2 unpend
467 #define NVIC_UNPEND0_INT1 0x00000002 ///< Interrupt 1 unpend
468 #define NVIC_UNPEND0_INT0 0x00000001 ///< Interrupt 0 unpend
472 * The following are defines for the bit fields in the NVIC_UNPEND1 register.
475 #define NVIC_UNPEND1_INT59 0x08000000 ///< Interrupt 59 unpend
476 #define NVIC_UNPEND1_INT58 0x04000000 ///< Interrupt 58 unpend
477 #define NVIC_UNPEND1_INT57 0x02000000 ///< Interrupt 57 unpend
478 #define NVIC_UNPEND1_INT56 0x01000000 ///< Interrupt 56 unpend
479 #define NVIC_UNPEND1_INT55 0x00800000 ///< Interrupt 55 unpend
480 #define NVIC_UNPEND1_INT54 0x00400000 ///< Interrupt 54 unpend
481 #define NVIC_UNPEND1_INT53 0x00200000 ///< Interrupt 53 unpend
482 #define NVIC_UNPEND1_INT52 0x00100000 ///< Interrupt 52 unpend
483 #define NVIC_UNPEND1_INT51 0x00080000 ///< Interrupt 51 unpend
484 #define NVIC_UNPEND1_INT50 0x00040000 ///< Interrupt 50 unpend
485 #define NVIC_UNPEND1_INT49 0x00020000 ///< Interrupt 49 unpend
486 #define NVIC_UNPEND1_INT48 0x00010000 ///< Interrupt 48 unpend
487 #define NVIC_UNPEND1_INT47 0x00008000 ///< Interrupt 47 unpend
488 #define NVIC_UNPEND1_INT46 0x00004000 ///< Interrupt 46 unpend
489 #define NVIC_UNPEND1_INT45 0x00002000 ///< Interrupt 45 unpend
490 #define NVIC_UNPEND1_INT44 0x00001000 ///< Interrupt 44 unpend
491 #define NVIC_UNPEND1_INT43 0x00000800 ///< Interrupt 43 unpend
492 #define NVIC_UNPEND1_INT42 0x00000400 ///< Interrupt 42 unpend
493 #define NVIC_UNPEND1_INT41 0x00000200 ///< Interrupt 41 unpend
494 #define NVIC_UNPEND1_INT40 0x00000100 ///< Interrupt 40 unpend
495 #define NVIC_UNPEND1_INT39 0x00000080 ///< Interrupt 39 unpend
496 #define NVIC_UNPEND1_INT38 0x00000040 ///< Interrupt 38 unpend
497 #define NVIC_UNPEND1_INT37 0x00000020 ///< Interrupt 37 unpend
498 #define NVIC_UNPEND1_INT36 0x00000010 ///< Interrupt 36 unpend
499 #define NVIC_UNPEND1_INT35 0x00000008 ///< Interrupt 35 unpend
500 #define NVIC_UNPEND1_INT34 0x00000004 ///< Interrupt 34 unpend
501 #define NVIC_UNPEND1_INT33 0x00000002 ///< Interrupt 33 unpend
502 #define NVIC_UNPEND1_INT32 0x00000001 ///< Interrupt 32 unpend
506 * The following are defines for the bit fields in the NVIC_ACTIVE0 register.
509 #define NVIC_ACTIVE0_INT31 0x80000000 ///< Interrupt 31 active
510 #define NVIC_ACTIVE0_INT30 0x40000000 ///< Interrupt 30 active
511 #define NVIC_ACTIVE0_INT29 0x20000000 ///< Interrupt 29 active
512 #define NVIC_ACTIVE0_INT28 0x10000000 ///< Interrupt 28 active
513 #define NVIC_ACTIVE0_INT27 0x08000000 ///< Interrupt 27 active
514 #define NVIC_ACTIVE0_INT26 0x04000000 ///< Interrupt 26 active
515 #define NVIC_ACTIVE0_INT25 0x02000000 ///< Interrupt 25 active
516 #define NVIC_ACTIVE0_INT24 0x01000000 ///< Interrupt 24 active
517 #define NVIC_ACTIVE0_INT23 0x00800000 ///< Interrupt 23 active
518 #define NVIC_ACTIVE0_INT22 0x00400000 ///< Interrupt 22 active
519 #define NVIC_ACTIVE0_INT21 0x00200000 ///< Interrupt 21 active
520 #define NVIC_ACTIVE0_INT20 0x00100000 ///< Interrupt 20 active
521 #define NVIC_ACTIVE0_INT19 0x00080000 ///< Interrupt 19 active
522 #define NVIC_ACTIVE0_INT18 0x00040000 ///< Interrupt 18 active
523 #define NVIC_ACTIVE0_INT17 0x00020000 ///< Interrupt 17 active
524 #define NVIC_ACTIVE0_INT16 0x00010000 ///< Interrupt 16 active
525 #define NVIC_ACTIVE0_INT15 0x00008000 ///< Interrupt 15 active
526 #define NVIC_ACTIVE0_INT14 0x00004000 ///< Interrupt 14 active
527 #define NVIC_ACTIVE0_INT13 0x00002000 ///< Interrupt 13 active
528 #define NVIC_ACTIVE0_INT12 0x00001000 ///< Interrupt 12 active
529 #define NVIC_ACTIVE0_INT11 0x00000800 ///< Interrupt 11 active
530 #define NVIC_ACTIVE0_INT10 0x00000400 ///< Interrupt 10 active
531 #define NVIC_ACTIVE0_INT9 0x00000200 ///< Interrupt 9 active
532 #define NVIC_ACTIVE0_INT8 0x00000100 ///< Interrupt 8 active
533 #define NVIC_ACTIVE0_INT7 0x00000080 ///< Interrupt 7 active
534 #define NVIC_ACTIVE0_INT6 0x00000040 ///< Interrupt 6 active
535 #define NVIC_ACTIVE0_INT5 0x00000020 ///< Interrupt 5 active
536 #define NVIC_ACTIVE0_INT4 0x00000010 ///< Interrupt 4 active
537 #define NVIC_ACTIVE0_INT3 0x00000008 ///< Interrupt 3 active
538 #define NVIC_ACTIVE0_INT2 0x00000004 ///< Interrupt 2 active
539 #define NVIC_ACTIVE0_INT1 0x00000002 ///< Interrupt 1 active
540 #define NVIC_ACTIVE0_INT0 0x00000001 ///< Interrupt 0 active
544 * The following are defines for the bit fields in the NVIC_ACTIVE1 register.
547 #define NVIC_ACTIVE1_INT59 0x08000000 ///< Interrupt 59 active
548 #define NVIC_ACTIVE1_INT58 0x04000000 ///< Interrupt 58 active
549 #define NVIC_ACTIVE1_INT57 0x02000000 ///< Interrupt 57 active
550 #define NVIC_ACTIVE1_INT56 0x01000000 ///< Interrupt 56 active
551 #define NVIC_ACTIVE1_INT55 0x00800000 ///< Interrupt 55 active
552 #define NVIC_ACTIVE1_INT54 0x00400000 ///< Interrupt 54 active
553 #define NVIC_ACTIVE1_INT53 0x00200000 ///< Interrupt 53 active
554 #define NVIC_ACTIVE1_INT52 0x00100000 ///< Interrupt 52 active
555 #define NVIC_ACTIVE1_INT51 0x00080000 ///< Interrupt 51 active
556 #define NVIC_ACTIVE1_INT50 0x00040000 ///< Interrupt 50 active
557 #define NVIC_ACTIVE1_INT49 0x00020000 ///< Interrupt 49 active
558 #define NVIC_ACTIVE1_INT48 0x00010000 ///< Interrupt 48 active
559 #define NVIC_ACTIVE1_INT47 0x00008000 ///< Interrupt 47 active
560 #define NVIC_ACTIVE1_INT46 0x00004000 ///< Interrupt 46 active
561 #define NVIC_ACTIVE1_INT45 0x00002000 ///< Interrupt 45 active
562 #define NVIC_ACTIVE1_INT44 0x00001000 ///< Interrupt 44 active
563 #define NVIC_ACTIVE1_INT43 0x00000800 ///< Interrupt 43 active
564 #define NVIC_ACTIVE1_INT42 0x00000400 ///< Interrupt 42 active
565 #define NVIC_ACTIVE1_INT41 0x00000200 ///< Interrupt 41 active
566 #define NVIC_ACTIVE1_INT40 0x00000100 ///< Interrupt 40 active
567 #define NVIC_ACTIVE1_INT39 0x00000080 ///< Interrupt 39 active
568 #define NVIC_ACTIVE1_INT38 0x00000040 ///< Interrupt 38 active
569 #define NVIC_ACTIVE1_INT37 0x00000020 ///< Interrupt 37 active
570 #define NVIC_ACTIVE1_INT36 0x00000010 ///< Interrupt 36 active
571 #define NVIC_ACTIVE1_INT35 0x00000008 ///< Interrupt 35 active
572 #define NVIC_ACTIVE1_INT34 0x00000004 ///< Interrupt 34 active
573 #define NVIC_ACTIVE1_INT33 0x00000002 ///< Interrupt 33 active
574 #define NVIC_ACTIVE1_INT32 0x00000001 ///< Interrupt 32 active
578 * The following are defines for the bit fields in the NVIC_PRI0 register.
581 #define NVIC_PRI0_INT3_M 0xFF000000 ///< Interrupt 3 priority mask
582 #define NVIC_PRI0_INT2_M 0x00FF0000 ///< Interrupt 2 priority mask
583 #define NVIC_PRI0_INT1_M 0x0000FF00 ///< Interrupt 1 priority mask
584 #define NVIC_PRI0_INT0_M 0x000000FF ///< Interrupt 0 priority mask
585 #define NVIC_PRI0_INT3_S 24
586 #define NVIC_PRI0_INT2_S 16
587 #define NVIC_PRI0_INT1_S 8
588 #define NVIC_PRI0_INT0_S 0
592 * The following are defines for the bit fields in the NVIC_PRI1 register.
595 #define NVIC_PRI1_INT7_M 0xFF000000 ///< Interrupt 7 priority mask
596 #define NVIC_PRI1_INT6_M 0x00FF0000 ///< Interrupt 6 priority mask
597 #define NVIC_PRI1_INT5_M 0x0000FF00 ///< Interrupt 5 priority mask
598 #define NVIC_PRI1_INT4_M 0x000000FF ///< Interrupt 4 priority mask
599 #define NVIC_PRI1_INT7_S 24
600 #define NVIC_PRI1_INT6_S 16
601 #define NVIC_PRI1_INT5_S 8
602 #define NVIC_PRI1_INT4_S 0
606 * The following are defines for the bit fields in the NVIC_PRI2 register.
609 #define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
610 #define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
611 #define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
612 #define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
613 #define NVIC_PRI2_INT11_S 24
614 #define NVIC_PRI2_INT10_S 16
615 #define NVIC_PRI2_INT9_S 8
616 #define NVIC_PRI2_INT8_S 0
620 * The following are defines for the bit fields in the NVIC_PRI3 register.
623 #define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
624 #define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
625 #define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
626 #define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
627 #define NVIC_PRI3_INT15_S 24
628 #define NVIC_PRI3_INT14_S 16
629 #define NVIC_PRI3_INT13_S 8
630 #define NVIC_PRI3_INT12_S 0
634 * The following are defines for the bit fields in the NVIC_PRI4 register.
637 #define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
638 #define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
639 #define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
640 #define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
641 #define NVIC_PRI4_INT19_S 24
642 #define NVIC_PRI4_INT18_S 16
643 #define NVIC_PRI4_INT17_S 8
644 #define NVIC_PRI4_INT16_S 0
648 * The following are defines for the bit fields in the NVIC_PRI5 register.
651 #define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
652 #define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
653 #define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
654 #define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
655 #define NVIC_PRI5_INT23_S 24
656 #define NVIC_PRI5_INT22_S 16
657 #define NVIC_PRI5_INT21_S 8
658 #define NVIC_PRI5_INT20_S 0
662 * The following are defines for the bit fields in the NVIC_PRI6 register.
665 #define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
666 #define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
667 #define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
668 #define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
669 #define NVIC_PRI6_INT27_S 24
670 #define NVIC_PRI6_INT26_S 16
671 #define NVIC_PRI6_INT25_S 8
672 #define NVIC_PRI6_INT24_S 0
676 * The following are defines for the bit fields in the NVIC_PRI7 register.
679 #define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
680 #define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
681 #define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
682 #define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
683 #define NVIC_PRI7_INT31_S 24
684 #define NVIC_PRI7_INT30_S 16
685 #define NVIC_PRI7_INT29_S 8
686 #define NVIC_PRI7_INT28_S 0
690 * The following are defines for the bit fields in the NVIC_PRI8 register.
693 #define NVIC_PRI8_INT35_M 0xFF000000 ///< Interrupt 35 priority mask
694 #define NVIC_PRI8_INT34_M 0x00FF0000 ///< Interrupt 34 priority mask
695 #define NVIC_PRI8_INT33_M 0x0000FF00 ///< Interrupt 33 priority mask
696 #define NVIC_PRI8_INT32_M 0x000000FF ///< Interrupt 32 priority mask
697 #define NVIC_PRI8_INT35_S 24
698 #define NVIC_PRI8_INT34_S 16
699 #define NVIC_PRI8_INT33_S 8
700 #define NVIC_PRI8_INT32_S 0
704 * The following are defines for the bit fields in the NVIC_PRI9 register.
707 #define NVIC_PRI9_INT39_M 0xFF000000 ///< Interrupt 39 priority mask
708 #define NVIC_PRI9_INT38_M 0x00FF0000 ///< Interrupt 38 priority mask
709 #define NVIC_PRI9_INT37_M 0x0000FF00 ///< Interrupt 37 priority mask
710 #define NVIC_PRI9_INT36_M 0x000000FF ///< Interrupt 36 priority mask
711 #define NVIC_PRI9_INT39_S 24
712 #define NVIC_PRI9_INT38_S 16
713 #define NVIC_PRI9_INT37_S 8
714 #define NVIC_PRI9_INT36_S 0
718 * The following are defines for the bit fields in the NVIC_PRI10 register.
721 #define NVIC_PRI10_INT43_M 0xFF000000 ///< Interrupt 43 priority mask
722 #define NVIC_PRI10_INT42_M 0x00FF0000 ///< Interrupt 42 priority mask
723 #define NVIC_PRI10_INT41_M 0x0000FF00 ///< Interrupt 41 priority mask
724 #define NVIC_PRI10_INT40_M 0x000000FF ///< Interrupt 40 priority mask
725 #define NVIC_PRI10_INT43_S 24
726 #define NVIC_PRI10_INT42_S 16
727 #define NVIC_PRI10_INT41_S 8
728 #define NVIC_PRI10_INT40_S 0
732 * The following are defines for the bit fields in the NVIC_CPUID register.
735 #define NVIC_CPUID_IMP_M 0xFF000000 ///< Implementer
736 #define NVIC_CPUID_VAR_M 0x00F00000 ///< Variant
737 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 ///< Processor part number
738 #define NVIC_CPUID_REV_M 0x0000000F ///< Revision
742 * The following are defines for the bit fields in the NVIC_INT_CTRL register.
745 #define NVIC_INT_CTRL_NMI_SET 0x80000000 ///< Pend a NMI
746 #define NVIC_INT_CTRL_PEND_SV 0x10000000 ///< Pend a PendSV
747 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 ///< Unpend a PendSV
748 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 ///< Set pending SysTick interrupt
749 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 ///< Clear pending SysTick interrupt
750 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 ///< Debug interrupt handling
751 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 ///< Debug interrupt pending
752 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 ///< Highest pending exception
753 #define NVIC_INT_CTRL_RET_BASE 0x00000800 ///< Return to base
754 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF ///< Current active exception
755 #define NVIC_INT_CTRL_VEC_PEN_S 12
756 #define NVIC_INT_CTRL_VEC_ACT_S 0
760 * The following are defines for the bit fields in the NVIC_VTABLE register.
763 #define NVIC_VTABLE_BASE 0x20000000 ///< Vector table base
764 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 ///< Vector table offset
765 #define NVIC_VTABLE_OFFSET_S 8
769 * The following are defines for the bit fields in the NVIC_APINT register.
772 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 ///< Vector key mask
773 #define NVIC_APINT_VECTKEY 0x05FA0000 ///< Vector key
774 #define NVIC_APINT_ENDIANESS 0x00008000 ///< Data endianess
775 #define NVIC_APINT_PRIGROUP_M 0x00000700 ///< Priority group
776 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 ///< Priority group 0.8 split
777 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 ///< Priority group 1.7 split
778 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 ///< Priority group 2.6 split
779 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 ///< Priority group 3.5 split
780 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 ///< Priority group 4.4 split
781 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 ///< Priority group 5.3 split
782 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 ///< Priority group 6.2 split
783 #define NVIC_APINT_SYSRESETREQ 0x00000004 ///< System reset request
784 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 ///< Clear active NMI/fault info
785 #define NVIC_APINT_VECT_RESET 0x00000001 ///< System reset
786 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 ///< Priority group 7.1 split
790 * The following are defines for the bit fields in the NVIC_SYS_CTRL register.
793 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 ///< Wakeup on pend
794 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 ///< Deep sleep enable
795 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 ///< Sleep on ISR exit
799 * The following are defines for the bit fields in the NVIC_CFG_CTRL register.
802 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 ///< Ignore bus fault in NMI/fault
803 #define NVIC_CFG_CTRL_DIV0 0x00000010 ///< Trap on divide by 0
804 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 ///< Trap on unaligned access
805 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 ///< Allow deep interrupt trigger
806 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 ///< Allow main interrupt trigger
807 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 ///< Thread state control
811 * The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
814 #define NVIC_SYS_PRI1_RES_M 0xFF000000 ///< Priority of reserved handler
815 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 ///< Priority of usage fault handler
816 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 ///< Priority of bus fault handler
817 #define NVIC_SYS_PRI1_MEM_M 0x000000FF ///< Priority of mem manage handler
818 #define NVIC_SYS_PRI1_USAGE_S 16
819 #define NVIC_SYS_PRI1_BUS_S 8
820 #define NVIC_SYS_PRI1_MEM_S 0
824 * The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
827 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 ///< Priority of SVCall handler
828 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF ///< Priority of reserved handlers
829 #define NVIC_SYS_PRI2_SVC_S 24
833 * The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
836 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 ///< Priority of Sys Tick handler
837 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 ///< Priority of PendSV handler
838 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 ///< Priority of reserved handler
839 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF ///< Priority of debug handler
840 #define NVIC_SYS_PRI3_TICK_S 24
841 #define NVIC_SYS_PRI3_PENDSV_S 16
842 #define NVIC_SYS_PRI3_DEBUG_S 0
846 * The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
850 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 ///< Usage fault enable
851 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 ///< Bus fault enable
852 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 ///< Mem manage fault enable
853 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 ///< SVCall is pended
854 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 ///< Bus fault is pended
855 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 ///< Sys tick is active
856 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 ///< PendSV is active
857 #define NVIC_SYS_HND_CTRL_MON 0x00000100 ///< Monitor is active
858 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 ///< SVCall is active
859 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 ///< Usage fault is active
860 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 ///< Bus fault is active
861 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 ///< Mem manage is active
865 * The following are defines for the bit fields in the NVIC_FAULT_STAT
869 #define NVIC_FAULT_STAT_DIV0 0x02000000 ///< Divide by zero fault
870 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 ///< Unaligned access fault
871 #define NVIC_FAULT_STAT_NOCP 0x00080000 ///< No coprocessor fault
872 #define NVIC_FAULT_STAT_INVPC 0x00040000 ///< Invalid PC fault
873 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 ///< Invalid state fault
874 #define NVIC_FAULT_STAT_UNDEF 0x00010000 ///< Undefined instruction fault
875 #define NVIC_FAULT_STAT_BFARV 0x00008000 ///< BFAR is valid
876 #define NVIC_FAULT_STAT_BSTKE 0x00001000 ///< Stack bus fault
877 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 ///< Unstack bus fault
878 #define NVIC_FAULT_STAT_IMPRE 0x00000400 ///< Imprecise data bus error
879 #define NVIC_FAULT_STAT_PRECISE 0x00000200 ///< Precise data bus error
880 #define NVIC_FAULT_STAT_IBUS 0x00000100 ///< Instruction bus fault
881 #define NVIC_FAULT_STAT_MMARV 0x00000080 ///< MMAR is valid
882 #define NVIC_FAULT_STAT_MSTKE 0x00000010 ///< Stack access violation
883 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 ///< Unstack access violation
884 #define NVIC_FAULT_STAT_DERR 0x00000002 ///< Data access violation
885 #define NVIC_FAULT_STAT_IERR 0x00000001 ///< Instruction access violation
889 * The following are defines for the bit fields in the NVIC_HFAULT_STAT
893 #define NVIC_HFAULT_STAT_DBG 0x80000000 ///< Debug event
894 #define NVIC_HFAULT_STAT_FORCED 0x40000000 ///< Cannot execute fault handler
895 #define NVIC_HFAULT_STAT_VECT 0x00000002 ///< Vector table read fault
899 * The following are defines for the bit fields in the NVIC_DEBUG_STAT
903 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 ///< EDBGRQ asserted
904 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 ///< Vector catch
905 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 ///< DWT match
906 #define NVIC_DEBUG_STAT_BKPT 0x00000002 ///< Breakpoint instruction
907 #define NVIC_DEBUG_STAT_HALTED 0x00000001 ///< Halt request
911 * The following are defines for the bit fields in the NVIC_MM_ADDR register.
914 #define NVIC_MM_ADDR_M 0xFFFFFFFF ///< Data fault address
915 #define NVIC_MM_ADDR_S 0
919 * The following are defines for the bit fields in the NVIC_FAULT_ADDR
923 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF ///< Data bus fault address
924 #define NVIC_FAULT_ADDR_S 0
928 * The following are defines for the bit fields in the NVIC_MPU_TYPE register.
931 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 ///< Number of I regions
932 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 ///< Number of D regions
933 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 ///< Separate or unified MPU
934 #define NVIC_MPU_TYPE_IREGION_S 16
935 #define NVIC_MPU_TYPE_DREGION_S 8
939 * The following are defines for the bit fields in the NVIC_MPU_CTRL register.
942 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 ///< MPU default region in priv mode
943 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 ///< MPU enabled during faults
944 #define NVIC_MPU_CTRL_ENABLE 0x00000001 ///< MPU enable
948 * The following are defines for the bit fields in the NVIC_MPU_NUMBER
952 #define NVIC_MPU_NUMBER_M 0x000000FF ///< MPU region to access
953 #define NVIC_MPU_NUMBER_S 0
957 * The following are defines for the bit fields in the NVIC_MPU_BASE register.
960 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 ///< Base address mask
961 #define NVIC_MPU_BASE_VALID 0x00000010 ///< Region number valid
962 #define NVIC_MPU_BASE_REGION_M 0x0000000F ///< Region number
963 #define NVIC_MPU_BASE_ADDR_S 8
964 #define NVIC_MPU_BASE_REGION_S 0
968 * The following are defines for the bit fields in the NVIC_MPU_ATTR register.
971 #define NVIC_MPU_ATTR_M 0xFFFF0000 ///< Attributes
972 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 ///< prv: no access, usr: no access
973 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 ///< Bufferable
974 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 ///< Cacheable
975 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 ///< Shareable
976 #define NVIC_MPU_ATTR_TEX_M 0x00380000 ///< Type extension mask
977 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 ///< prv: rw, usr: none
978 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 ///< prv: rw, usr: read-only
979 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 ///< prv: rw, usr: rw
980 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 ///< prv: ro, usr: none
981 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 ///< prv: ro, usr: ro
982 #define NVIC_MPU_ATTR_AP_M 0x07000000 ///< Access permissions mask
983 #define NVIC_MPU_ATTR_XN 0x10000000 ///< Execute disable
984 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 ///< Sub-region disable mask
985 #define NVIC_MPU_ATTR_SRD_0 0x00000100 ///< Sub-region 0 disable
986 #define NVIC_MPU_ATTR_SRD_1 0x00000200 ///< Sub-region 1 disable
987 #define NVIC_MPU_ATTR_SRD_2 0x00000400 ///< Sub-region 2 disable
988 #define NVIC_MPU_ATTR_SRD_3 0x00000800 ///< Sub-region 3 disable
989 #define NVIC_MPU_ATTR_SRD_4 0x00001000 ///< Sub-region 4 disable
990 #define NVIC_MPU_ATTR_SRD_5 0x00002000 ///< Sub-region 5 disable
991 #define NVIC_MPU_ATTR_SRD_6 0x00004000 ///< Sub-region 6 disable
992 #define NVIC_MPU_ATTR_SRD_7 0x00008000 ///< Sub-region 7 disable
993 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E ///< Region size mask
994 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 ///< Region size 32 bytes
995 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A ///< Region size 64 bytes
996 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C ///< Region size 128 bytes
997 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E ///< Region size 256 bytes
998 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 ///< Region size 512 bytes
999 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 ///< Region size 1 Kbytes
1000 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 ///< Region size 2 Kbytes
1001 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 ///< Region size 4 Kbytes
1002 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 ///< Region size 8 Kbytes
1003 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A ///< Region size 16 Kbytes
1004 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C ///< Region size 32 Kbytes
1005 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E ///< Region size 64 Kbytes
1006 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 ///< Region size 128 Kbytes
1007 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 ///< Region size 256 Kbytes
1008 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 ///< Region size 512 Kbytes
1009 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 ///< Region size 1 Mbytes
1010 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 ///< Region size 2 Mbytes
1011 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A ///< Region size 4 Mbytes
1012 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C ///< Region size 8 Mbytes
1013 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E ///< Region size 16 Mbytes
1014 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 ///< Region size 32 Mbytes
1015 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 ///< Region size 64 Mbytes
1016 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 ///< Region size 128 Mbytes
1017 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 ///< Region size 256 Mbytes
1018 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 ///< Region size 512 Mbytes
1019 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A ///< Region size 1 Gbytes
1020 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C ///< Region size 2 Gbytes
1021 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E ///< Region size 4 Gbytes
1022 #define NVIC_MPU_ATTR_ENABLE 0x00000001 ///< Region enable
1026 * The following are defines for the bit fields in the NVIC_DBG_CTRL register.
1029 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 ///< Debug key mask
1030 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 ///< Debug key
1031 #define NVIC_DBG_CTRL_S_RESET_ST \
1032 0x02000000 ///< Core has reset since last read
1033 #define NVIC_DBG_CTRL_S_RETIRE_ST \
1034 0x01000000 ///< Core has executed insruction
1035 ///< since last read
1036 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 ///< Core is locked up
1037 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 ///< Core is sleeping
1038 #define NVIC_DBG_CTRL_S_HALT 0x00020000 ///< Core status on halt
1039 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 ///< Register read/write available
1040 #define NVIC_DBG_CTRL_C_SNAPSTALL \
1041 0x00000020 ///< Breaks a stalled load/store
1042 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 ///< Mask interrupts when stepping
1043 #define NVIC_DBG_CTRL_C_STEP 0x00000004 ///< Step the core
1044 #define NVIC_DBG_CTRL_C_HALT 0x00000002 ///< Halt the core
1045 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 ///< Enable debug
1049 * The following are defines for the bit fields in the NVIC_DBG_XFER register.
1052 #define NVIC_DBG_XFER_REG_WNR 0x00010000 ///< Write or not read
1053 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F ///< Register
1054 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 ///< Control/Fault/BasePri/PriMask
1055 #define NVIC_DBG_XFER_REG_DSP 0x00000013 ///< Deep SP
1056 #define NVIC_DBG_XFER_REG_PSP 0x00000012 ///< Process SP
1057 #define NVIC_DBG_XFER_REG_MSP 0x00000011 ///< Main SP
1058 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 ///< xPSR/Flags register
1059 #define NVIC_DBG_XFER_REG_R15 0x0000000F ///< Register R15
1060 #define NVIC_DBG_XFER_REG_R14 0x0000000E ///< Register R14
1061 #define NVIC_DBG_XFER_REG_R13 0x0000000D ///< Register R13
1062 #define NVIC_DBG_XFER_REG_R12 0x0000000C ///< Register R12
1063 #define NVIC_DBG_XFER_REG_R11 0x0000000B ///< Register R11
1064 #define NVIC_DBG_XFER_REG_R10 0x0000000A ///< Register R10
1065 #define NVIC_DBG_XFER_REG_R9 0x00000009 ///< Register R9
1066 #define NVIC_DBG_XFER_REG_R8 0x00000008 ///< Register R8
1067 #define NVIC_DBG_XFER_REG_R7 0x00000007 ///< Register R7
1068 #define NVIC_DBG_XFER_REG_R6 0x00000006 ///< Register R6
1069 #define NVIC_DBG_XFER_REG_R5 0x00000005 ///< Register R5
1070 #define NVIC_DBG_XFER_REG_R4 0x00000004 ///< Register R4
1071 #define NVIC_DBG_XFER_REG_R3 0x00000003 ///< Register R3
1072 #define NVIC_DBG_XFER_REG_R2 0x00000002 ///< Register R2
1073 #define NVIC_DBG_XFER_REG_R1 0x00000001 ///< Register R1
1074 #define NVIC_DBG_XFER_REG_R0 0x00000000 ///< Register R0
1078 * The following are defines for the bit fields in the NVIC_DBG_DATA register.
1081 #define NVIC_DBG_DATA_M 0xFFFFFFFF ///< Data temporary cache
1082 #define NVIC_DBG_DATA_S 0
1086 * The following are defines for the bit fields in the NVIC_DBG_INT register.
1089 #define NVIC_DBG_INT_HARDERR 0x00000400 ///< Debug trap on hard fault
1090 #define NVIC_DBG_INT_INTERR 0x00000200 ///< Debug trap on interrupt errors
1091 #define NVIC_DBG_INT_BUSERR 0x00000100 ///< Debug trap on bus error
1092 #define NVIC_DBG_INT_STATERR 0x00000080 ///< Debug trap on usage fault state
1093 #define NVIC_DBG_INT_CHKERR 0x00000040 ///< Debug trap on usage fault check
1094 #define NVIC_DBG_INT_NOCPERR 0x00000020 ///< Debug trap on coprocessor error
1095 #define NVIC_DBG_INT_MMERR 0x00000010 ///< Debug trap on mem manage fault
1096 #define NVIC_DBG_INT_RESET 0x00000008 ///< Core reset status
1097 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 ///< Clear pending core reset
1098 #define NVIC_DBG_INT_RSTPENDING 0x00000002 ///< Core reset is pending
1099 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 ///< Reset vector catch
1103 * The following are defines for the bit fields in the NVIC_SW_TRIG register.
1106 #define NVIC_SW_TRIG_INTID_M 0x000003FF ///< Interrupt to trigger
1107 #define NVIC_SW_TRIG_INTID_S 0
1111 #endif /* STM32_NVIC_H */
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