4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief UART STM32F10xx registers definition.
42 #define USART_WORD_LEN_8B ((uint16_t)0x0000)
43 #define USART_WORD_LEN_9B ((uint16_t)0x1000)
48 #define USART_STOP_BIT_1 ((uint16_t)0x0000)
49 #define USART_STOP_BIT_0_5 ((uint16_t)0x1000)
50 #define USART_STOP_BIT_2 ((uint16_t)0x2000)
51 #define USART_STOP_BIT_1_5 ((uint16_t)0x3000)
56 #define USART_PARITY_NO ((uint16_t)0x0000)
57 #define USART_PARITY_EVEN ((uint16_t)0x0400)
58 #define USART_PARITY_ODD ((uint16_t)0x0600)
62 * USART Hardware Flow Control
64 #define USART_HW_FLOW_NONE ((uint16_t)0x0000)
65 #define USART_HW_FLOW_RTS ((uint16_t)0x0100)
66 #define USART_HW_FLOW_CTS ((uint16_t)0x0200)
67 #define USART_HW_FLOW_RTS_CTS ((uint16_t)0x0300)
73 #define USART_CLK_DIS ((uint16_t)0x0000)
74 #define USART_CLK_EN ((uint16_t)0x0800)
77 * USART Clock Polarity
79 #define USART_CPOL_LOW ((uint16_t)0x0000)
80 #define USART_CPOL_HIGHT ((uint16_t)0x0400)
85 #define USART_CPHA_1EDGE ((uint16_t)0x0000)
86 #define USART_CPHA_2EDGE ((uint16_t)0x0200)
91 * USART Interrupt definition
93 #define USART_IT_PE ((uint16_t)0x0028)
94 #define USART_IT_TXE ((uint16_t)0x0727)
95 #define USART_IT_TC ((uint16_t)0x0626)
96 #define USART_IT_RXNE ((uint16_t)0x0525)
97 #define USART_IT_IDLE ((uint16_t)0x0424)
98 #define USART_IT_LBD ((uint16_t)0x0846)
99 #define USART_IT_CTS ((uint16_t)0x096A)
100 #define USART_IT_ERR ((uint16_t)0x0060)
101 #define USART_IT_ORE ((uint16_t)0x0360)
102 #define USART_IT_NE ((uint16_t)0x0260)
103 #define USART_IT_FE ((uint16_t)0x0160)
106 #define INT_UART0_CR1 0x0C
107 #define INT_UART0_CR2 0x10
108 #define INT_UART0_CR3 0x14
113 #define USART_DMA_REQ_TX ((uint16_t)0x0080)
114 #define USART_DMA_REQ_RX ((uint16_t)0x0040)
117 * USART WakeUp methods
119 #define USART_WAKEUP_IDLELINE ((uint16_t)0x0000)
120 #define USART_WAKEUP_ADRESSMARK ((uint16_t)0x0800)
124 * USART LIN Break Detection Length
126 #define USART_LIN_BREAK_DET_LEN_10B ((uint16_t)0x0000)
127 #define USART_LIN_BREAK_DET_LEN_11B ((uint16_t)0x0020)
130 * USART IrDA Low Power
132 #define USART_IRDA_MODE_LOWPOWER ((uint16_t)0x0004)
133 #define USART_IRDA_MODE_NORMAL ((uint16_t)0x0000)
136 #define CR1_RUN_SET ((uint16_t)0x2000) /* USART Enable MASK */
137 #define CR1_RUN_RESET ((uint16_t)0xDFFF) /* USART Disable MASK */
138 #define CR1_RWU_SET ((uint16_t)0x0002) /* USART mute mode Enable MASK */
139 #define CR1_RWU_RESET ((uint16_t)0xFFFD) /* USART mute mode Enable MASK */
140 #define CR1_SBK_SET ((uint16_t)0x0001) /* USART Break Character send MASK */
141 #define CR1_USART_CLEAR_MASK ((uint16_t)0xE9F3) /* USART CR1 MASK */
157 #define CR2_MASK ((uint16_t)0xFFF0) /* USART address MASK */
158 #define CR2_LINE_SET ((uint16_t)0x4000) /* USART LIN Enable MASK */
159 #define CR2_LINE_RESET ((uint16_t)0xBFFF) /* USART LIN Disable MASK */
160 #define CR2_USART_CLEAR_MASK ((uint16_t)0xC0FF) /* USART CR2 MASK */
162 #define CR3_SCEN_SET ((uint16_t)0x0020) /* USART SC Enable MASK */
163 #define CR3_SCEN_RESET ((uint16_t)0xFFDF) /* USART SC Disable MASK */
164 #define CR3_NACK_SET ((uint16_t)0x0010) /* USART SC NACK Enable MASK */
165 #define CR3_NACK_RESET ((uint16_t)0xFFEF) /* USART SC NACK Disable MASK */
166 #define CR3_HDSEL_SET ((uint16_t)0x0008) /* USART Half-Duplex Enable MASK */
167 #define CR3_HDSEL_RESET ((uint16_t)0xFFF7) /* USART Half-Duplex Disable MASK */
168 #define CR3_IRLP_MASK ((uint16_t)0xFFFB) /* USART IrDA LowPower mode MASK */
169 #define CR3_LBDL_MASK ((uint16_t)0xFFDF) /* USART LIN Break detection MASK */
170 #define CR3_WAKE_MASK ((uint16_t)0xF7FF) /* USART WakeUp Method MASK */
171 #define CR3_IREN_SET ((uint16_t)0x0002) /* USART IrDA Enable MASK */
172 #define CR3_IREN_RESET ((uint16_t)0xFFFD) /* USART IrDA Disable MASK */
173 #define CR3_CLEAR_MASK ((uint16_t)0xFCFF) /* USART CR3 MASK */
188 #define GTPR_LSB_MASK ((uint16_t)0x00FF) /* Guard Time Register LSB MASK */
189 #define GTPR_MSB_MASK ((uint16_t)0xFF00) /* Guard Time Register MSB MASK */
191 #define USART_IT_MASK ((uint16_t)0x001F) /* USART Interrupt MASK */
194 #define USART_FLAG_CTS ((uint16_t)0x0200)
195 #define USART_FLAG_LBD ((uint16_t)0x0100)
196 #define USART_FLAG_TXE ((uint16_t)0x0080)
197 #define USART_FLAG_TC ((uint16_t)0x0040)
198 #define USART_FLAG_RXNE ((uint16_t)0x0020)
199 #define USART_FLAG_IDLE ((uint16_t)0x0010)
200 #define USART_FLAG_ORE ((uint16_t)0x0008)
201 #define USART_FLAG_NE ((uint16_t)0x0004)
202 #define USART_FLAG_FE ((uint16_t)0x0002)
203 #define USART_FLAG_PE ((uint16_t)0x0001)
204 #define USART_FLAG_MASK ((uint16_t)0x03FF)
207 /* USART registers */
227 #define USART_MODE_RX ((uint16_t)0x0004)
228 #define USART_MODE_TX ((uint16_t)0x0008)
231 #define USART_LASTBIT_DISABLE ((uint16_t)0x0000)
232 #define USART_LASTBIT_ENABLE ((uint16_t)0x0100)
235 INLINE uint16_t evaluate_brr(struct stm32_usart *base, unsigned long cpu_freq, unsigned long baud)
237 uint32_t freq, reg, div, frac;
239 /* NOTE: PCLK1 has been configured as CPU_FREQ / 2 */
240 freq = (base == (struct stm32_usart *)USART1_BASE) ? cpu_freq : cpu_freq / 2;
241 div = (0x19 * freq) / (0x04 * baud);
242 reg = (div / 0x64) << 0x04;
243 frac = div - (0x64 * (reg >> 0x04));
244 reg |= ((frac * 0x10 + 0x32) / 0x64) & 0x0f;
246 return (uint16_t)reg;
249 #endif /* STM32_UART_H */