4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU detection through special preprocessor macros
39 #if defined(__ARM_ARCH_4T__) /* GCC */ \
40 || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */
43 #define CPU_CORE_NAME "ARM7TDMI"
45 // AT91SAM7S core family
46 #if defined(__ARM_AT91SAM7S32__)
47 #define CPU_ARM_AT91 1
48 #define CPU_ARM_AT91SAM7S32 1
49 #define CPU_NAME "AT91SAM7S32"
51 #define CPU_ARM_AT91SAM7S32 0
54 #if defined(__ARM_AT91SAM7S64__)
55 #define CPU_ARM_AT91 1
56 #define CPU_ARM_SAM7S_LARGE 1
57 #define CPU_ARM_AT91SAM7S64 1
58 #define CPU_NAME "AT91SAM7S64"
60 #define CPU_ARM_AT91SAM7S64 0
63 #if defined(__ARM_AT91SAM7S128__)
64 #define CPU_ARM_AT91 1
65 #define CPU_ARM_SAM7S_LARGE 1
66 #define CPU_ARM_AT91SAM7S128 1
67 #define CPU_NAME "AT91SAM7S128"
69 #define CPU_ARM_AT91SAM7S128 0
72 #if defined(__ARM_AT91SAM7S256__)
73 #define CPU_ARM_AT91 1
74 #define CPU_ARM_SAM7S_LARGE 1
75 #define CPU_ARM_AT91SAM7S256 1
76 #define CPU_NAME "AT91SAM7S256"
78 #define CPU_ARM_AT91SAM7S256 0
81 #if defined(__ARM_AT91SAM7S512__)
82 #define CPU_ARM_AT91 1
83 #define CPU_ARM_SAM7S_LARGE 1
84 #define CPU_ARM_AT91SAM7S512 1
85 #define CPU_NAME "AT91SAM7S512"
87 #define CPU_ARM_AT91SAM7S512 0
90 // AT91SAM7X core family
91 #if defined(__ARM_AT91SAM7X128__)
92 #define CPU_ARM_AT91 1
93 #define CPU_ARM_SAM7X 1
94 #define CPU_ARM_AT91SAM7X128 1
95 #define CPU_NAME "AT91SAM7X128"
97 #define CPU_ARM_AT91SAM7X128 0
100 #if defined(__ARM_AT91SAM7X256__)
101 #define CPU_ARM_AT91 1
102 #define CPU_ARM_SAM7X 1
103 #define CPU_ARM_AT91SAM7X256 1
104 #define CPU_NAME "AT91SAM7X256"
106 #define CPU_ARM_AT91SAM7X256 0
110 #if defined(__ARM_AT91SAM7X512__)
111 #define CPU_ARM_AT91 1
112 #define CPU_ARM_SAM7X 1
113 #define CPU_ARM_AT91SAM7X512 1
114 #define CPU_NAME "AT91SAM7X512"
116 #define CPU_ARM_AT91SAM7X512 0
119 #if defined(__ARM_LPC2378__)
120 #define CPU_ARM_LPC2 1
121 #define CPU_ARM_LPC2378 1
122 #define CPU_NAME "LPC2378"
124 #define CPU_ARM_LPC2378 0
127 #if !defined(CPU_ARM_SAM7S_LARGE)
128 #define CPU_ARM_SAM7S_LARGE 0
131 #if !defined(CPU_ARM_SAM7X)
132 #define CPU_ARM_SAM7X 0
136 #if defined(CPU_ARM_AT91)
137 #if CPU_ARM_AT91SAM7S32 + CPU_ARM_AT91SAM7S64 \
138 + CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 \
139 + CPU_ARM_AT91SAM7S512 \
140 + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 \
141 + CPU_ARM_AT91SAM7X512 != 1
142 #error ARM CPU configuration error
144 #define CPU_ARM_LPC2 0
146 #elif defined (CPU_ARM_LPC2)
148 #if CPU_ARM_LPC2378 + 0 != 1
149 #error NXP LPC2xxx ARM CPU configuration error
151 #define CPU_ARM_AT91 0
152 /* #elif Add other ARM families here */
154 #define CPU_ARM_AT91 0
155 #define CPU_ARM_LPC2 0
159 #if CPU_ARM_AT91 + CPU_ARM_LPC2 + 0 /* Add other ARM families here */ != 1
160 #error ARM CPU configuration error
166 #define CPU_ARM_AT91 0
167 #define CPU_ARM_LPC2 0
169 /* SAM7 sub-families */
170 #define CPU_ARM_SAM7S_LARGE 0
171 #define CPU_ARM_SAM7X 0
174 #define CPU_ARM_AT91SAM7S32 0
175 #define CPU_ARM_AT91SAM7S64 0
176 #define CPU_ARM_AT91SAM7S128 0
177 #define CPU_ARM_AT91SAM7S256 0
178 #define CPU_ARM_AT91SAM7S512 0
179 #define CPU_ARM_AT91SAM7X128 0
180 #define CPU_ARM_AT91SAM7X256 0
181 #define CPU_ARM_AT91SAM7X512 0
183 #define CPU_ARM_LPC2378 0
186 #if defined(__ARM_ARCH_7M__)
190 #define CPU_CORE_NAME "Cortex-M3"
192 #if defined (__ARM_LM3S1968__)
193 #define CPU_CM3_LM3S 1
194 #define CPU_CM3_LM3S1968 1
195 #define CPU_NAME "LM3S1968"
197 #define CPU_CM3_LM3S1968 0
200 #if defined (__ARM_LM3S8962__)
201 #define CPU_CM3_LM3S 1
202 #define CPU_CM3_LM3S8962 1
203 #define CPU_NAME "LM3S8962"
205 #define CPU_CM3_LM3S8962 0
208 #if defined (__ARM_STM32F101C4__)
209 #define CPU_CM3_STM32 1
210 #define CPU_CM3_STM32F101C4 1
211 #define CPU_NAME "STM32F101C4"
213 #define CPU_CM3_STM32F101C4 0
216 #if defined (__ARM_STM32F103RB__)
217 #define CPU_CM3_STM32 1
218 #define CPU_CM3_STM32F103RB 1
219 #define CPU_NAME "STM32F103RB"
221 #define CPU_CM3_STM32F103RB 0
224 #if defined (__ARM_SAM3N4__)
225 #define CPU_CM3_SAM3 1
226 #define CPU_CM3_SAM3N 1
227 #define CPU_CM3_SAM3N4 1
228 #define CPU_NAME "SAM3N4"
230 #define CPU_CM3_SAM3S 0
231 #define CPU_CM3_SAM3U 0
232 #define CPU_CM3_SAM3N2 0
233 #define CPU_CM3_SAM3N1 0
234 #define CPU_CM3_SAM3X 0
236 #define CPU_CM3_SAM3N4 0
239 #if defined (__ARM_SAM3S4__)
240 #define CPU_CM3_SAM3 1
241 #define CPU_CM3_SAM3S 1
242 #define CPU_CM3_SAM3S4 1
243 #define CPU_NAME "SAM3S4"
245 #define CPU_CM3_SAM3N 0
246 #define CPU_CM3_SAM3U 0
247 #define CPU_CM3_SAM3X 0
249 #define CPU_CM3_SAM3S4 0
252 #if defined (__ARM_SAM3U4__)
253 #define CPU_CM3_SAM3 1
254 #define CPU_CM3_SAM3U 1
255 #define CPU_CM3_SAM3U4 1
256 #define CPU_NAME "SAM3U4"
258 #define CPU_CM3_SAM3N 0
259 #define CPU_CM3_SAM3S 0
260 #define CPU_CM3_SAM3X 0
262 #define CPU_CM3_SAM3U4 0
265 #if defined (__ARM_SAM3X8__)
266 #define CPU_CM3_SAM3 1
267 #define CPU_CM3_SAM3X 1
268 #define CPU_CM3_SAM3X8 1
269 #define CPU_NAME "SAM3X8"
271 #define CPU_CM3_SAM3N 0
272 #define CPU_CM3_SAM3S 0
273 #define CPU_CM3_SAM3U 0
275 #define CPU_CM3_SAM3X8 0
278 #if defined (CPU_CM3_LM3S)
279 #if CPU_CM3_LM3S1968 + CPU_CM3_LM3S8962 + 0 != 1
280 #error Luminary Cortex-M3 CPU configuration error
282 #define CPU_CM3_STM32 0
283 #define CPU_CM3_SAM3 0
284 #elif defined (CPU_CM3_STM32)
285 #if CPU_CM3_STM32F101C4 + CPU_CM3_STM32F103RB + 0 != 1
286 #error STM32 Cortex-M3 CPU configuration error
288 #define CPU_CM3_LM3S 0
289 #define CPU_CM3_SAM3 0
290 #elif defined (CPU_CM3_SAM3)
291 #if CPU_CM3_SAM3N + CPU_CM3_SAM3U + CPU_CM3_SAM3S + CPU_CM3_SAM3X + 0 != 1
292 #error SAM3 Cortex-M3 CPU configuration error
294 #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + CPU_CM3_SAM3X8 + 0 != 1
295 #error SAM3 Cortex-M3 CPU configuration error
297 #define CPU_CM3_LM3S 0
298 #define CPU_CM3_STM32 0
299 /* #elif Add other Cortex-M3 families here */
301 #define CPU_CM3_LM3S 0
302 #define CPU_CM3_STM32 0
303 #define CPU_CM3_SAM3 0
307 #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1
308 #error Cortex-M3 CPU configuration error
313 #define CPU_CM3_LM3S 0
314 #define CPU_CM3_LM3S1968 0
315 #define CPU_CM3_LM3S8962 0
317 #define CPU_CM3_STM32 0
318 #define CPU_CM3_STM32F103RB 0
319 #define CPU_CM3_STM32F101C4 0
321 #define CPU_CM3_SAM3 0
322 #define CPU_CM3_SAM3N 0
323 #define CPU_CM3_SAM3N4 0
324 #define CPU_CM3_SAM3X 0
325 #define CPU_CM3_SAM3X8 0
328 #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \
329 && !defined(__ARM4TM__) /* IAR: if not ARM assume I196 */
330 #warning Assuming CPU is I196
337 #if defined(__i386__) /* GCC */ \
338 || (defined(_M_IX86) && !defined(_WIN64)) /* MSVC */
343 #define CPU_CORE_NAME "x86"
344 #define CPU_NAME "generic"
345 #elif defined(__x86_64__) /* GCC */ \
346 || (defined(_M_IX86) && defined(_WIN64)) /* MSVC */
351 #define CPU_CORE_NAME "x86_64"
352 #define CPU_NAME "generic"
359 #if defined (_ARCH_PPC) || defined(_ARCH_PPC64)
362 #if defined(_ARCH_PPC)
367 #if defined(_ARCH_PPC64)
378 #if defined(__m56800E__) || defined(__m56800__)
380 #define CPU_ID dsp56k
385 #if defined (__AVR__)
388 #define CPU_CORE_NAME "AVR"
390 #if defined(__AVR_ATmega32__)
391 #define CPU_AVR_ATMEGA32 1
392 #define CPU_NAME "ATmega32"
394 #define CPU_AVR_ATMEGA32 0
397 #if defined(__AVR_ATmega64__)
398 #define CPU_AVR_ATMEGA64 1
399 #define CPU_NAME "ATmega64"
401 #define CPU_AVR_ATMEGA64 0
404 #if defined(__AVR_ATmega103__)
405 #define CPU_AVR_ATMEGA103 1
406 #define CPU_NAME "ATmega103"
408 #define CPU_AVR_ATMEGA103 0
411 #if defined(__AVR_ATmega128__)
412 #define CPU_AVR_ATMEGA128 1
413 #define CPU_NAME "ATmega128"
415 #define CPU_AVR_ATMEGA128 0
418 #if defined(__AVR_ATmega8__)
419 #define CPU_AVR_ATMEGA8 1
420 #define CPU_NAME "ATmega8"
422 #define CPU_AVR_ATMEGA8 0
425 #if defined(__AVR_ATmega168__)
426 #define CPU_AVR_ATMEGA168 1
427 #define CPU_NAME "ATmega168"
429 #define CPU_AVR_ATMEGA168 0
432 #if defined(__AVR_ATmega328P__)
433 #define CPU_AVR_ATMEGA328P 1
434 #define CPU_NAME "ATmega328P"
436 #define CPU_AVR_ATMEGA328P 0
439 #if defined(__AVR_ATmega1281__)
440 #define CPU_AVR_ATMEGA1281 1
441 #define CPU_NAME "ATmega1281"
443 #define CPU_AVR_ATMEGA1281 0
446 #if defined(__AVR_ATmega1280__)
447 #define CPU_AVR_ATMEGA1280 1
448 #define CPU_NAME "ATmega1280"
450 #define CPU_AVR_ATMEGA1280 0
453 #if defined(__AVR_ATmega2560__)
454 #define CPU_AVR_ATMEGA2560 1
455 #define CPU_NAME "ATmega2560"
457 #define CPU_AVR_ATMEGA2560 0
460 #if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \
461 + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 \
462 + CPU_AVR_ATMEGA1280 + CPU_AVR_ATMEGA2560 != 1
463 #error AVR CPU configuration error
467 #define CPU_AVR_ATMEGA8 0
468 #define CPU_AVR_ATMEGA168 0
469 #define CPU_AVR_ATMEGA328P 0
470 #define CPU_AVR_ATMEGA32 0
471 #define CPU_AVR_ATMEGA64 0
472 #define CPU_AVR_ATMEGA103 0
473 #define CPU_AVR_ATMEGA128 0
474 #define CPU_AVR_ATMEGA1281 0
475 #define CPU_AVR_ATMEGA1280 0
476 #define CPU_AVR_ATMEGA2560 0
479 #if defined (__MSP430__)
481 #define CPU_ID msp430
482 #define CPU_CORE_NAME "MSP430"
484 #if defined(__MSP430F2274__)
485 #define CPU_MSP430F2274 1
486 #define CPU_NAME "MSP430F2274"
488 #define CPU_MSP430F2274 0
491 #if defined(__MSP430G2231__)
492 #define CPU_MSP430G2231 1
493 #define CPU_NAME "MSP430G2231"
495 #define CPU_MSP430G2231 0
498 #if CPU_MSP430F2274 + CPU_MSP430G2231 != 1
499 #error MSP430 CPU configuration error
503 #define CPU_MSP430F2274 0
504 #define CPU_MSP430G2231 0
508 /* Self-check for the detection: only one CPU must be detected */
509 #if CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 == 0
511 #elif !defined(CPU_ID)
512 #error CPU_ID not defined
513 #elif CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 != 1
514 #error Internal CPU configuration error
518 #endif /* CPU_DETECT_H */