AT91SAM3 port: initial support for AT91SAM3 (mainly kdebug and register defs), tested...
[bertos.git] / bertos / cpu / detect.h
1 /**
2  * \file
3  * <!--
4  * This file is part of BeRTOS.
5  *
6  * Bertos is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  *
20  * As a special exception, you may use this file as part of a free software
21  * library without restriction.  Specifically, if other files instantiate
22  * templates or use macros or inline functions from this file, or you compile
23  * this file and link it with other files to produce an executable, this
24  * file does not by itself cause the resulting executable to be covered by
25  * the GNU General Public License.  This exception does not however
26  * invalidate any other reasons why the executable file might be covered by
27  * the GNU General Public License.
28  *
29  * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30  * Copyright 2004 Giovanni Bajo
31  *
32  * -->
33  *
34  * \brief CPU detection through special preprocessor macros
35  */
36 #ifndef CPU_DETECT_H
37 #define CPU_DETECT_H
38
39 #if defined(__ARM_ARCH_4T__) /* GCC */ \
40         || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */
41         #define CPU_ARM 1
42         #define CPU_ID  arm
43
44         // AT91SAM7S core family
45         #if defined(__ARM_AT91SAM7S32__)
46                 #define CPU_ARM_AT91         1
47                 #define CPU_ARM_AT91SAM7S32  1
48         #else
49                 #define CPU_ARM_AT91SAM7S32  0
50         #endif
51
52         #if defined(__ARM_AT91SAM7S64__)
53                 #define CPU_ARM_AT91         1
54                 #define CPU_ARM_SAM7S_LARGE  1
55                 #define CPU_ARM_AT91SAM7S64  1
56         #else
57                 #define CPU_ARM_AT91SAM7S64  0
58         #endif
59
60         #if defined(__ARM_AT91SAM7S128__)
61                 #define CPU_ARM_AT91         1
62                 #define CPU_ARM_SAM7S_LARGE  1
63                 #define CPU_ARM_AT91SAM7S128 1
64         #else
65                 #define CPU_ARM_AT91SAM7S128 0
66         #endif
67
68         #if defined(__ARM_AT91SAM7S256__)
69                 #define CPU_ARM_AT91         1
70                 #define CPU_ARM_SAM7S_LARGE  1
71                 #define CPU_ARM_AT91SAM7S256 1
72         #else
73                 #define CPU_ARM_AT91SAM7S256 0
74         #endif
75
76         #if defined(__ARM_AT91SAM7S512__)
77                 #define CPU_ARM_AT91         1
78                 #define CPU_ARM_SAM7S_LARGE  1
79                 #define CPU_ARM_AT91SAM7S512 1
80         #else
81                 #define CPU_ARM_AT91SAM7S512 0
82         #endif
83
84         // AT91SAM7X core family
85         #if defined(__ARM_AT91SAM7X128__)
86                 #define CPU_ARM_AT91         1
87                 #define CPU_ARM_SAM7X        1
88                 #define CPU_ARM_AT91SAM7X128 1
89         #else
90                 #define CPU_ARM_AT91SAM7X128 0
91         #endif
92
93         #if defined(__ARM_AT91SAM7X256__)
94                 #define CPU_ARM_AT91         1
95                 #define CPU_ARM_SAM7X        1
96                 #define CPU_ARM_AT91SAM7X256 1
97         #else
98                 #define CPU_ARM_AT91SAM7X256 0
99         #endif
100
101
102         #if defined(__ARM_AT91SAM7X512__)
103                 #define CPU_ARM_AT91         1
104                 #define CPU_ARM_SAM7X        1
105                 #define CPU_ARM_AT91SAM7X512 1
106         #else
107                 #define CPU_ARM_AT91SAM7X512 0
108         #endif
109
110         #if defined(__ARM_LPC2378__)
111                 #define CPU_ARM_LPC2        1
112                 #define CPU_ARM_LPC2378     1
113         #else
114                 #define CPU_ARM_LPC2378     0
115         #endif
116
117         #if !defined(CPU_ARM_SAM7S_LARGE)
118                 #define CPU_ARM_SAM7S_LARGE 0
119         #endif
120
121         #if !defined(CPU_ARM_SAM7X)
122                 #define CPU_ARM_SAM7X 0
123         #endif
124
125
126         #if defined(CPU_ARM_AT91)
127                 #if CPU_ARM_AT91SAM7S32 + CPU_ARM_AT91SAM7S64 \
128                 + CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 \
129                 + CPU_ARM_AT91SAM7S512 \
130                 + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 \
131                 + CPU_ARM_AT91SAM7X512 != 1
132                         #error ARM CPU configuration error
133                 #endif
134                 #define CPU_ARM_LPC2        0
135
136         #elif defined (CPU_ARM_LPC2)
137
138                 #if CPU_ARM_LPC2378 + 0 != 1
139                         #error NXP LPC2xxx ARM CPU configuration error
140                 #endif
141                 #define CPU_ARM_AT91        0
142         /* #elif Add other ARM families here */
143         #else
144                 #define CPU_ARM_AT91        0
145                 #define CPU_ARM_LPC2        0
146         #endif
147
148
149         #if CPU_ARM_AT91 + CPU_ARM_LPC2 + 0 /* Add other ARM families here */ != 1
150                 #error ARM CPU configuration error
151         #endif
152 #else
153         #define CPU_ARM                 0
154
155         /* ARM Families */
156         #define CPU_ARM_AT91            0
157         #define CPU_ARM_LPC2            0
158
159         /* SAM7 sub-families */
160         #define CPU_ARM_SAM7S_LARGE     0
161         #define CPU_ARM_SAM7X           0
162
163         /* ARM CPUs */
164         #define CPU_ARM_AT91SAM7S32     0
165         #define CPU_ARM_AT91SAM7S64     0
166         #define CPU_ARM_AT91SAM7S128    0
167         #define CPU_ARM_AT91SAM7S256    0
168         #define CPU_ARM_AT91SAM7S512    0
169         #define CPU_ARM_AT91SAM7X128    0
170         #define CPU_ARM_AT91SAM7X256    0
171         #define CPU_ARM_AT91SAM7X512    0
172
173         #define CPU_ARM_LPC2378         0
174 #endif
175
176 #if defined(__ARM_ARCH_7M__)
177         /* Cortex-M3 */
178         #define CPU_CM3 1
179         #define CPU_ID  cm3
180
181         #if defined (__ARM_LM3S1968__)
182                 #define CPU_CM3_LM3S        1
183                 #define CPU_CM3_LM3S1968    1
184         #else
185                 #define CPU_CM3_LM3S1968    0
186         #endif
187
188         #if defined (__ARM_LM3S8962__)
189                 #define CPU_CM3_LM3S        1
190                 #define CPU_CM3_LM3S8962    1
191         #else
192                 #define CPU_CM3_LM3S8962    0
193         #endif
194
195         #if defined (__ARM_STM32F103RB__)
196                 #define CPU_CM3_STM32       1
197                 #define CPU_CM3_STM32F103RB 1
198         #else
199                 #define CPU_CM3_STM32F103RB 0
200         #endif
201
202         #if defined (__ARM_AT91SAM3N4__)
203                 #define CPU_CM3_AT91SAM3    1
204                 #define CPU_CM3_AT91SAM3N   1
205                 #define CPU_CM3_AT91SAM3N4  1
206         #else
207                 #define CPU_CM3_AT91SAM3N4  0
208         #endif
209
210         #if defined (CPU_CM3_LM3S)
211                 #if CPU_CM3_LM3S1968 + CPU_CM3_LM3S8962 + 0 != 1
212                         #error Luminary Cortex-M3 CPU configuration error
213                 #endif
214                 #define CPU_CM3_STM32       0
215                 #define CPU_CM3_AT91SAM3    0
216         #elif defined (CPU_CM3_STM32)
217                 #if CPU_CM3_STM32F103RB + 0 != 1
218                         #error STM32 Cortex-M3 CPU configuration error
219                 #endif
220                 #define CPU_CM3_LM3S        0
221                 #define CPU_CM3_AT91SAM3    0
222         #elif defined (CPU_CM3_AT91SAM3)
223                 #if CPU_CM3_AT91SAM3N + 0 != 1
224                         #error AT91SAM3 Cortex-M3 CPU configuration error
225                 #endif
226                 #if CPU_CM3_AT91SAM3N4 + 0 != 1
227                         #error AT91SAM3 Cortex-M3 CPU configuration error
228                 #endif
229                 #define CPU_CM3_LM3S        0
230                 #define CPU_CM3_STM32       0
231         /* #elif Add other Cortex-M3 families here */
232         #else
233                 #define CPU_CM3_LM3S        0
234                 #define CPU_CM3_STM32       0
235                 #define CPU_CM3_AT91SAM3    0
236         #endif
237
238
239         #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_AT91SAM3 + 0 /* Add other Cortex-M3 families here */ != 1
240                 #error Cortex-M3 CPU configuration error
241         #endif
242
243 #else
244         #define CPU_CM3 0
245         #define CPU_CM3_LM3S 0
246         #define CPU_CM3_LM3S1968 0
247         #define CPU_CM3_LM3S8968 0
248
249         #define CPU_CM3_STM32 0
250         #define CPU_CM3_STM32F103RB 0
251
252         #define CPU_CM3_AT91SAM3 0
253         #define CPU_CM3_AT91SAM3N 0
254         #define CPU_CM3_AT91SAM3N4 0
255 #endif
256
257 #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \
258         && !defined(__ARM4TM__) /* IAR: if not ARM assume I196 */
259         #warning Assuming CPU is I196
260         #define CPU_I196                1
261         #define CPU_ID                  i196
262 #else
263         #define CPU_I196                0
264 #endif
265
266 #if defined(__i386__) /* GCC */ \
267         || (defined(_M_IX86) && !defined(_WIN64)) /* MSVC */
268         #define CPU_X86                 1
269         #define CPU_X86_32              1
270         #define CPU_X86_64              0
271         #define CPU_ID                  x86
272 #elif defined(__x86_64__) /* GCC */ \
273         || (defined(_M_IX86) && defined(_WIN64)) /* MSVC */
274         #define CPU_X86                 1
275         #define CPU_X86_32              0
276         #define CPU_X86_64              1
277         #define CPU_ID                  x86
278 #else
279         #define CPU_X86                 0
280         #define CPU_I386                0
281         #define CPU_X86_64              0
282 #endif
283
284 #if defined (_ARCH_PPC) || defined(_ARCH_PPC64)
285         #define CPU_PPC                 1
286         #define CPU_ID                  ppc
287         #if defined(_ARCH_PPC)
288                 #define CPU_PPC32       1
289         #else
290                 #define CPU_PPC32       0
291         #endif
292         #if defined(_ARCH_PPC64)
293                 #define CPU_PPC64       1
294         #else
295                 #define CPU_PPC64       0
296         #endif
297 #else
298         #define CPU_PPC                 0
299         #define CPU_PPC32               0
300         #define CPU_PPC64               0
301 #endif
302
303 #if defined(__m56800E__) || defined(__m56800__)
304         #define CPU_DSP56K              1
305         #define CPU_ID                  dsp56k
306 #else
307         #define CPU_DSP56K              0
308 #endif
309
310 #if defined (__AVR__)
311         #define CPU_AVR                 1
312         #define CPU_ID                  avr
313
314         #if defined(__AVR_ATmega32__)
315                 #define CPU_AVR_ATMEGA32    1
316         #else
317                 #define CPU_AVR_ATMEGA32    0
318         #endif
319
320         #if defined(__AVR_ATmega64__)
321                 #define CPU_AVR_ATMEGA64    1
322         #else
323                 #define CPU_AVR_ATMEGA64    0
324         #endif
325
326         #if defined(__AVR_ATmega103__)
327                 #define CPU_AVR_ATMEGA103   1
328         #else
329                 #define CPU_AVR_ATMEGA103   0
330         #endif
331
332         #if defined(__AVR_ATmega128__)
333                 #define CPU_AVR_ATMEGA128   1
334         #else
335                 #define CPU_AVR_ATMEGA128   0
336         #endif
337
338         #if defined(__AVR_ATmega8__)
339                 #define CPU_AVR_ATMEGA8     1
340         #else
341                 #define CPU_AVR_ATMEGA8     0
342         #endif
343
344         #if defined(__AVR_ATmega168__)
345                 #define CPU_AVR_ATMEGA168   1
346         #else
347                 #define CPU_AVR_ATMEGA168   0
348         #endif
349
350         #if defined(__AVR_ATmega328P__)
351                 #define CPU_AVR_ATMEGA328P   1
352         #else
353                 #define CPU_AVR_ATMEGA328P   0
354         #endif
355
356         #if defined(__AVR_ATmega1281__)
357                 #define CPU_AVR_ATMEGA1281  1
358         #else
359                 #define CPU_AVR_ATMEGA1281  0
360         #endif
361
362         #if defined(__AVR_ATmega1280__)
363                 #define CPU_AVR_ATMEGA1280  1
364         #else
365                 #define CPU_AVR_ATMEGA1280  0
366         #endif
367
368         #if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \
369           + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 \
370           + CPU_AVR_ATMEGA1280 != 1
371                 #error AVR CPU configuration error
372         #endif
373 #else
374         #define CPU_AVR                 0
375         #define CPU_AVR_ATMEGA8         0
376         #define CPU_AVR_ATMEGA168       0
377         #define CPU_AVR_ATMEGA328P      0
378         #define CPU_AVR_ATMEGA32        0
379         #define CPU_AVR_ATMEGA64        0
380         #define CPU_AVR_ATMEGA103       0
381         #define CPU_AVR_ATMEGA128       0
382         #define CPU_AVR_ATMEGA1281      0
383         #define CPU_AVR_ATMEGA1280      0
384 #endif
385
386 #if defined (__MSP430__)
387         #define CPU_MSP430              1
388         #define CPU_ID                  msp430
389
390         #if defined(__MSP430_2274__)
391                 #define CPU_MSP430_2274     1
392         #else
393                 #define CPU_MSP430_2274     0
394         #endif
395 #else
396         #define CPU_MSP430              0
397 #endif
398
399
400 /* Self-check for the detection: only one CPU must be detected */
401 #if CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 == 0
402         #error Unknown CPU
403 #elif !defined(CPU_ID)
404         #error CPU_ID not defined
405 #elif CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 != 1
406         #error Internal CPU configuration error
407 #endif
408
409
410 #endif /* CPU_DETECT_H */