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29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
34 * \author Stefano Fedrigo <aleph@develer.com>
35 * \author Giovanni Bajo <rasky@develer.com>
37 * \brief DSP5680x CPU specific serial I/O driver
42 #include <drv/ser_p.h>
44 #include <cfg/debug.h>
46 #include <DSP56F807.h>
48 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
49 // the serial, we need to disable the GPIO functions on them.
50 #define REG_GPIO_SERIAL_0 REG_GPIO_E
51 #define REG_GPIO_SERIAL_MASK_0 0x03
53 #define REG_GPIO_SERIAL_1 REG_GPIO_D
54 #define REG_GPIO_SERIAL_MASK_1 0xC0
57 // Check flag consistency
58 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
59 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
60 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
61 (SERRF_NOISEERROR != REG_SCI_SR_NF)
62 #error error flags do not match with register bits
65 static unsigned char ser0_fifo_rx[CONFIG_SER0_FIFOSIZE_RX];
66 static unsigned char ser0_fifo_tx[CONFIG_SER0_FIFOSIZE_TX];
67 static unsigned char ser1_fifo_rx[CONFIG_SER1_FIFOSIZE_RX];
68 static unsigned char ser1_fifo_tx[CONFIG_SER1_FIFOSIZE_TX];
73 #define MAX_MULTI_GROUPS 1
75 struct Semaphore multi_sems[MAX_MULTI_GROUPS];
81 struct SerialHardware hw;
82 struct Serial* serial;
83 volatile struct REG_SCI_STRUCT* regs;
90 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
92 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
95 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
97 regs->CR |= REG_SCI_CR_RIE;
100 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
102 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
105 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
107 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
110 static inline void disable_tx_irq(struct SerialHardware* _hw)
112 struct SCI* hw = (struct SCI*)_hw;
114 disable_tx_irq_bare(hw->regs);
117 static inline void disable_rx_irq(struct SerialHardware* _hw)
119 struct SCI* hw = (struct SCI*)_hw;
121 disable_rx_irq_bare(hw->regs);
124 static inline void enable_tx_irq(struct SerialHardware* _hw)
126 struct SCI* hw = (struct SCI*)_hw;
128 enable_tx_irq_bare(hw->regs);
131 static inline void enable_rx_irq(struct SerialHardware* _hw)
133 struct SCI* hw = (struct SCI*)_hw;
135 enable_rx_irq_bare(hw->regs);
138 static inline bool tx_irq_enabled(struct SerialHardware* _hw)
140 struct SCI* hw = (struct SCI*)_hw;
142 return (hw->regs->CR & REG_SCI_CR_TEIE);
145 static void tx_isr(const struct SCI *hw)
147 #pragma interrupt warn
148 volatile struct REG_SCI_STRUCT* regs = hw->regs;
150 if (fifo_isempty(&hw->serial->txfifo))
151 disable_tx_irq_bare(regs);
154 // Clear transmitter flags before sending data
156 regs->DR = fifo_pop(&hw->serial->txfifo);
160 static void rx_isr(const struct SCI *hw)
162 #pragma interrupt warn
163 volatile struct REG_SCI_STRUCT* regs = hw->regs;
166 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
172 * Serial IRQ can happen for two reason: data ready (RDRF) or overrun (OR)
173 * If the data is ready, we need to fetch it from the data register or
174 * the interrupt will retrigger immediatly. In case of overrun, instead,
175 * the value of the data register is meaningless.
177 if (regs->SR & REG_SCI_SR_RDRF)
179 unsigned char data = regs->DR;
181 if (fifo_isfull(&hw->serial->rxfifo))
182 hw->serial->status |= SERRF_RXFIFOOVERRUN;
184 fifo_push(&hw->serial->rxfifo, data);
187 // Writing anything to the status register clear the error bits.
191 static void init(struct SerialHardware* _hw, struct Serial* ser)
193 struct SCI* hw = (struct SCI*)_hw;
194 volatile struct REG_SCI_STRUCT* regs = hw->regs;
196 // Clear status register (IRQ/status flags)
200 // Clear data register
203 // Install the handlers and set priorities for both IRQs
204 irq_install(hw->irq_tx, (isr_t)tx_isr, hw);
205 irq_install(hw->irq_rx, (isr_t)rx_isr, hw);
206 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
207 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
209 // Activate the RX error interrupts, and RX/TX transmissions
210 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
211 enable_rx_irq_bare(regs);
213 // Disable GPIO pins for TX and RX lines
214 // \todo this should be divided into serial 0 and 1
215 REG_GPIO_SERIAL_0->PER |= REG_GPIO_SERIAL_MASK_0;
216 REG_GPIO_SERIAL_1->PER |= REG_GPIO_SERIAL_MASK_1;
221 static void cleanup(struct SerialHardware* _hw)
223 struct SCI* hw = (struct SCI*)_hw;
225 // Uninstall the ISRs
228 irq_uninstall(hw->irq_tx);
229 irq_uninstall(hw->irq_rx);
232 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
234 struct SCI* hw = (struct SCI*)_hw;
236 // SCI has an internal 16x divider on the input clock, which comes
237 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
238 // it to calculate the period to store in the register.
239 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
242 static void setparity(struct SerialHardware* _hw, int parity)
251 static void multi_init(void)
253 static bool flag = false;
259 for (i = 0; i < MAX_MULTI_GROUPS; ++i)
260 sem_init(&multi_sems[i]);
264 static void init_lock(struct SerialHardware* _hw, struct Serial *ser)
266 struct SCI* hw = (struct SCI*)_hw;
268 // Initialize the multi engine (if needed)
271 // Acquire the lock of the semaphore for this group
272 ASSERT(hw->num_group >= 0);
273 ASSERT(hw->num_group < MAX_MULTI_GROUPS);
274 sem_obtain(&multi_sems[hw->num_group]);
276 // Do a hardware switch to the given serial
277 ser_hw_switch(hw->num_group, hw->id);
282 static void cleanup_unlock(struct SerialHardware* _hw)
284 struct SCI* hw = (struct SCI*)_hw;
288 sem_release(&multi_sems[hw->num_group]);
291 #endif /* CONFIG_SER_MULTI */
294 static const struct SerialHardwareVT SCI_VT =
298 .setBaudrate = setbaudrate,
299 .setParity = setparity,
300 .txStart = enable_tx_irq,
301 .txSending = tx_irq_enabled,
305 static const struct SerialHardwareVT SCI_MULTI_VT =
308 .cleanup = cleanup_unlock,
309 .setBaudrate = setbaudrate,
310 .setParity = setparity,
311 .txStart = enable_tx_irq,
312 .txSending = tx_irq_enabled,
314 #endif /* CONFIG_SER_MULTI */
316 #define SCI_DESC_NORMAL(hwch) \
321 .rxbuffer = ser ## hwch ## _fifo_rx, \
322 .txbuffer = ser ## hwch ## _fifo_tx, \
323 .rxbuffer_size = countof(ser ## hwch ## _fifo_rx), \
324 .txbuffer_size = countof(ser ## hwch ## _fifo_tx), \
326 .regs = ®_SCI[hwch], \
327 .irq_rx = IRQ_SCI ## hwch ## _RECEIVER_FULL, \
328 .irq_tx = IRQ_SCI ## hwch ## _TRANSMITTER_READY, \
335 #define SCI_DESC_MULTI(hwch, group_, id_) \
339 .table = &SCI_MULTI_VT, \
340 .rxbuffer = ser ## hwch ## _fifo_rx, \
341 .txbuffer = ser ## hwch ## _fifo_tx, \
342 .rxbuffer_size = countof(ser ## hwch ## _fifo_rx), \
343 .txbuffer_size = countof(ser ## hwch ## _fifo_tx), \
345 .regs = ®_SCI[hwch], \
346 .irq_rx = IRQ_SCI ## hwch ## _RECEIVER_FULL, \
347 .irq_tx = IRQ_SCI ## hwch ## _TRANSMITTER_READY, \
348 .num_group = group_, \
352 #endif /* CONFIG_SER_MULTI */
354 // \todo Move this into hw.h, with a little preprocessor magic
355 static struct SCI SCIDescs[] =
358 SCI_DESC_MULTI(1, 0, 0),
359 SCI_DESC_MULTI(1, 0, 1),
362 struct SerialHardware* ser_hw_getdesc(int unit)
364 ASSERT(unit < countof(SCIDescs));
365 return &SCIDescs[unit].hw;