sam3: add register definitions for RSTC and EMAC
[bertos.git] / bertos / cpu / frame.h
1 /**
2  * \file
3  * <!--
4  * This file is part of BeRTOS.
5  *
6  * Bertos is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  *
20  * As a special exception, you may use this file as part of a free software
21  * library without restriction.  Specifically, if other files instantiate
22  * templates or use macros or inline functions from this file, or you compile
23  * this file and link it with other files to produce an executable, this
24  * file does not by itself cause the resulting executable to be covered by
25  * the GNU General Public License.  This exception does not however
26  * invalidate any other reasons why the executable file might be covered by
27  * the GNU General Public License.
28  *
29  * Copyright 2008 Bernie Innocenti <bernie@codewiz.org>
30  * Copyright 2004, 2005, 2006, 2007, 2008 Develer S.r.l. (http://www.develer.com/)
31  * Copyright 2004 Giovanni Bajo
32  *
33  * -->
34  *
35  * \brief CPU-specific stack frame handling macros.
36  *
37  * These are mainly used by the portable part of the scheduler
38  * to work with the process stack frames.
39  *
40  * \author Giovanni Bajo <rasky@develer.com>
41  * \author Bernie Innocenti <bernie@codewiz.org>
42  * \author Stefano Fedrigo <aleph@develer.com>
43  * \author Francesco Sacchi <batt@develer.com>
44  */
45 #ifndef CPU_FRAME_H
46 #define CPU_FRAME_H
47
48 #include <cpu/detect.h>
49
50 #include "cfg/cfg_arch.h"      /* ARCH_EMUL */
51 #include <cfg/compiler.h>      /* for uintXX_t */
52
53 #if CPU_X86
54         #if CPU_X86_32
55                 #define CPU_SAVED_REGS_CNT      2
56         #elif CPU_X86_64
57                 #define CPU_SAVED_REGS_CNT      8
58         #else
59                 #error "unknown CPU"
60         #endif
61         #define CPU_STACK_GROWS_UPWARD  0
62         #define CPU_SP_ON_EMPTY_SLOT    0
63
64 #elif CPU_ARM
65
66         #define CPU_SAVED_REGS_CNT     8
67         #define CPU_STACK_GROWS_UPWARD 0
68         #define CPU_SP_ON_EMPTY_SLOT   0
69
70 #elif CPU_CM3
71
72         #define CPU_SAVED_REGS_CNT     8
73         #define CPU_STACK_GROWS_UPWARD 0
74         #define CPU_SP_ON_EMPTY_SLOT   0
75
76 #elif CPU_PPC
77
78         #define CPU_SAVED_REGS_CNT     1
79         #define CPU_STACK_GROWS_UPWARD 0
80         #define CPU_SP_ON_EMPTY_SLOT   1
81
82 #elif CPU_DSP56K
83
84         #define CPU_SAVED_REGS_CNT      8
85         #define CPU_STACK_GROWS_UPWARD  1
86         #define CPU_SP_ON_EMPTY_SLOT    0
87
88 #elif CPU_AVR
89
90         #define CPU_SAVED_REGS_CNT     18
91         #define CPU_STACK_GROWS_UPWARD  0
92         #define CPU_SP_ON_EMPTY_SLOT    1
93
94 #elif CPU_MSP430
95
96         #define CPU_SAVED_REGS_CNT     16
97         #define CPU_STACK_GROWS_UPWARD  1
98         #define CPU_SP_ON_EMPTY_SLOT    0
99
100 #else
101         #error No CPU_... defined.
102 #endif
103
104 #ifndef CPU_STACK_GROWS_UPWARD
105         #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
106 #endif
107
108 #ifndef CPU_SP_ON_EMPTY_SLOT
109         #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
110 #endif
111
112 /// Default for macro not defined in the right arch section
113 #ifndef CPU_REG_INIT_VALUE
114         #define CPU_REG_INIT_VALUE(reg)     (reg)
115 #endif
116
117 /*
118  * Support stack handling peculiarities of a few CPUs.
119  *
120  * Most processors let their stack grow downward and
121  * keep SP pointing at the last pushed value.
122  */
123 #if !CPU_STACK_GROWS_UPWARD
124         #if !CPU_SP_ON_EMPTY_SLOT
125                 /* Most microprocessors (x86, m68k...) */
126                 #define CPU_PUSH_WORD(sp, data) \
127                         do { *--(sp) = (data); } while (0)
128                 #define CPU_POP_WORD(sp) \
129                         (*(sp)++)
130         #else
131                 /* AVR insanity */
132                 #define CPU_PUSH_WORD(sp, data) \
133                         do { *(sp)-- = (data); } while (0)
134                 #define CPU_POP_WORD(sp) \
135                         (*++(sp))
136         #endif
137
138 #else /* CPU_STACK_GROWS_UPWARD */
139
140         #if !CPU_SP_ON_EMPTY_SLOT
141                 /* DSP56K and other weirdos */
142                 #define CPU_PUSH_WORD(sp, data) \
143                         do { *++(sp) = (cpu_stack_t)(data); } while (0)
144                 #define CPU_POP_WORD(sp) \
145                         (*(sp)--)
146         #else
147                 #error I bet you cannot find a CPU like this
148         #endif
149 #endif
150
151
152 #if CPU_DSP56K
153         /*
154          * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
155          * RTS discards SR while returning (it does not restore it). So we push
156          * 0 to fake the same context.
157          */
158         #define CPU_PUSH_CALL_FRAME(sp, func) \
159                 do { \
160                         CPU_PUSH_WORD((sp), (func)); \
161                         CPU_PUSH_WORD((sp), 0x100); \
162                 } while (0);
163
164 #elif CPU_CM3
165
166         #if CONFIG_KERN_PREEMPT
167                 INLINE void cm3_preempt_switch_context(cpu_stack_t **new_sp, cpu_stack_t **old_sp)
168                 {
169                         register cpu_stack_t **__new_sp asm ("r0") = new_sp;
170                         register cpu_stack_t **__old_sp asm ("r1") = old_sp;
171
172                         asm volatile ("svc #0"
173                                 : : "r"(__new_sp), "r"(__old_sp) : "memory", "cc");
174                 }
175                 #define asm_switch_context cm3_preempt_switch_context
176
177                 #define CPU_CREATE_NEW_STACK(stack) \
178                         do { \
179                                 size_t i; \
180                                 /* Initialize process stack frame */ \
181                                 CPU_PUSH_WORD((stack), 0x01000000);             /* xPSR    */   \
182                                 CPU_PUSH_WORD((stack), (cpu_stack_t)proc_entry);        /* pc      */   \
183                                 CPU_PUSH_WORD((stack), 0);                              /* lr      */   \
184                                 CPU_PUSH_WORD((stack), 0);                              /* ip      */   \
185                                 CPU_PUSH_WORD((stack), 0);                              /* r3      */   \
186                                 CPU_PUSH_WORD((stack), 0);                              /* r2      */   \
187                                 CPU_PUSH_WORD((stack), 0);                              /* r1      */   \
188                                 CPU_PUSH_WORD((stack), 0);                              /* r0      */   \
189                                 CPU_PUSH_WORD((stack), 0xfffffffd);             /* lr_exc  */   \
190                                 /* Push a clean set of CPU registers for asm_switch_context() */ \
191                                 for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
192                                         CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \
193                                 CPU_PUSH_WORD(stack, IRQ_PRIO_DISABLED); \
194                         } while (0)
195
196         #endif /* CONFIG_KERN_PREEMPT */
197
198 #elif CPU_AVR
199         /*
200          * On AVR, addresses are pushed into the stack as little-endian, while
201          * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
202          * no natural endianess).
203          */
204         #define CPU_PUSH_CALL_FRAME(sp, func) \
205                 do { \
206                         uint16_t funcaddr = (uint16_t)(func); \
207                         CPU_PUSH_WORD((sp), funcaddr); \
208                         CPU_PUSH_WORD((sp), funcaddr>>8); \
209                 } while (0)
210
211         /*
212          * If the kernel is in idle-spinning, the processor executes:
213          *
214          * IRQ_ENABLE;
215          * CPU_IDLE;
216          * IRQ_DISABLE;
217          *
218          * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
219          * We could define CPU_IDLE to expand to none, so the resulting
220          * asm code would be:
221          *
222          * sei;
223          * cli;
224          *
225          * But Atmel datasheet states:
226          * "When using the SEI instruction to enable interrupts,
227          * the instruction following SEI will be executed *before*
228          * any pending interrupts", so "cli" is executed before any
229          * pending interrupt with the result that IRQs will *NOT*
230          * be enabled!
231          * To ensure that IRQ will run a NOP is required.
232          */
233         #define CPU_IDLE NOP
234
235 #elif CPU_PPC
236
237         #define CPU_PUSH_CALL_FRAME(sp, func) \
238                 do { \
239                         CPU_PUSH_WORD((sp), (cpu_stack_t)(func)); /* LR -> 8(SP) */ \
240                         CPU_PUSH_WORD((sp), 0);                  /* CR -> 4(SP) */ \
241                 } while (0)
242
243 #endif
244
245 #ifndef CPU_PUSH_CALL_FRAME
246         #define CPU_PUSH_CALL_FRAME(sp, func) \
247                 CPU_PUSH_WORD((sp), (cpu_stack_t)(func))
248 #endif
249
250 /**
251  * \def CPU_IDLE
252  *
253  * \brief Invoked by the scheduler to stop the CPU when idle.
254  *
255  * This hook can be redefined to put the CPU in low-power mode, or to
256  * profile system load with an external strobe, or to save CPU cycles
257  * in hosted environments such as emulators.
258  */
259 #ifndef CPU_IDLE
260         #define CPU_IDLE PAUSE
261 #endif /* !CPU_IDLE */
262
263 /**
264  * Default macro for creating a new Process stack
265  */
266 #ifndef CPU_CREATE_NEW_STACK
267
268         #define CPU_CREATE_NEW_STACK(stack) \
269                 do { \
270                         size_t i; \
271                         /* Initialize process stack frame */ \
272                         CPU_PUSH_CALL_FRAME(stack, proc_entry); \
273                         /* Push a clean set of CPU registers for asm_switch_context() */ \
274                         for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
275                                 CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \
276                 } while (0)
277 #endif
278
279 #endif /* CPU_ATTR_H */