4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific IRQ definitions.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernie Innocenti <bernie@codewiz.org>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
47 #include <kern/proc.h> /* proc_needPreempt() / proc_preempt() */
49 #include <cfg/compiler.h> /* for uintXX_t */
50 #include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */
53 #define IRQ_DISABLE disable_interrupt()
54 #define IRQ_ENABLE enable_interrupt()
57 /* Get IRQ_* definitions from the hosting environment. */
60 #define IRQ_DISABLE FIXME
61 #define IRQ_ENABLE FIXME
62 #define IRQ_SAVE_DISABLE(x) FIXME
63 #define IRQ_RESTORE(x) FIXME
64 #endif /* OS_EMBEDDED */
72 * NOTE: 0 means that an interrupt is not affected by the global IRQ
76 #define IRQ_PRIO_MIN 0xf0
77 #define IRQ_PRIO_MAX 0
79 * To disable interrupts we just raise the system base priority to a
80 * number lower than the default IRQ priority. In this way, all the
81 * "normal" interrupt can't be triggered. High-priority interrupt can
82 * still happen (at the moment only the soft-interrupt svcall uses a
83 * priority greater than the default IRQ priority).
85 * To enable interrupts we set the system base priority to 0, that
86 * means IRQ priority mechanism is disabled, and any interrupt can
89 #define IRQ_PRIO_DISABLED 0x40
90 #define IRQ_PRIO_ENABLED 0
94 register cpu_flags_t reg = IRQ_PRIO_DISABLED; \
97 : : "r"(reg) : "memory", "cc"); \
102 register cpu_flags_t reg = IRQ_PRIO_ENABLED; \
105 : : "r"(reg) : "memory", "cc"); \
108 #define CPU_READ_FLAGS() \
110 register cpu_flags_t reg; \
113 : "=r"(reg) : : "memory", "cc"); \
117 #define IRQ_SAVE_DISABLE(x) \
119 x = CPU_READ_FLAGS(); \
123 #define IRQ_RESTORE(x) \
127 : : "r"(x) : "memory", "cc"); \
130 #define IRQ_ENABLED() (CPU_READ_FLAGS() == IRQ_PRIO_ENABLED)
132 INLINE bool irq_running(void)
134 register uint32_t ret;
137 * Check if the current stack pointer is the main stack or
138 * process stack: we use the main stack only in Handler mode,
139 * so this means we're running inside an ISR.
146 "moveq %0, #1\n\t" : "=r"(ret) : : "cc");
149 #define IRQ_RUNNING() irq_running()
151 #if (CONFIG_KERN && CONFIG_KERN_PREEMPT)
153 #define DECLARE_ISR_CONTEXT_SWITCH(func) \
155 INLINE void __isr_##func(void); \
159 if (!proc_needPreempt()) \
162 * Set a PendSV request.
164 * The preemption handler will be called immediately
165 * after this ISR in tail-chaining mode (without the
166 * overhead of hardware state saving and restoration
167 * between interrupts).
169 HWREG(NVIC_INT_CTRL) = NVIC_INT_CTRL_PEND_SV; \
171 INLINE void __isr_##func(void)
174 * With task priorities enabled each ISR is used a point to
175 * check if we need to perform a context switch.
177 * Instead, without priorities a context switch can occur only
178 * when the running task expires its time quantum. In this last
179 * case, the context switch can only occur in the timer ISR,
180 * that must be always declared with the
181 * DECLARE_ISR_CONTEXT_SWITCH() macro.
184 #define DECLARE_ISR(func) \
185 DECLARE_ISR_CONTEXT_SWITCH(func)
187 * Interrupt service routine prototype: can be used for
188 * forward declarations.
190 #define ISR_PROTO(func) \
191 ISR_PROTO_CONTEXT_SWITCH(func)
192 #endif /* !CONFIG_KERN_PRI */
196 #define ISR_PROTO(func) void func(void)
199 #define DECLARE_ISR(func) void func(void)
201 #ifndef DECLARE_ISR_CONTEXT_SWITCH
202 #define DECLARE_ISR_CONTEXT_SWITCH(func) void func(void)
204 #ifndef ISR_PROTO_CONTEXT_SWITCH
205 #define ISR_PROTO_CONTEXT_SWITCH(func) void func(void)
210 #ifdef __IAR_SYSTEMS_ICC__
214 #if __CPU_MODE__ == 1 /* Thumb */
216 extern cpu_flags_t get_CPSR(void);
217 extern void set_CPSR(cpu_flags_t flags);
219 #define get_CPSR __get_CPSR
220 #define set_CPSR __set_CPSR
223 #define IRQ_DISABLE __disable_interrupt()
224 #define IRQ_ENABLE __enable_interrupt()
226 #define IRQ_SAVE_DISABLE(x) \
229 __disable_interrupt(); \
232 #define IRQ_RESTORE(x) \
237 #define IRQ_ENABLED() \
238 ((bool)(get_CPSR() & 0xb0))
240 #else /* !__IAR_SYSTEMS_ICC__ */
242 #define IRQ_DISABLE \
247 "orr %0, %0, #0xc0\n\t" \
248 "msr cpsr_c, %0\n\t" \
249 : "=r" (sreg) : : "memory", "cc"); \
257 "bic %0, %0, #0xc0\n\t" \
258 "msr cpsr_c, %0\n\t" \
259 : "=r" (sreg) : : "memory", "cc"); \
262 #define IRQ_SAVE_DISABLE(x) \
264 register cpu_flags_t sreg; \
267 "orr %1, %0, #0xc0\n\t" \
268 "msr cpsr_c, %1\n\t" \
269 : "=r" (x), "=r" (sreg) \
270 : : "memory", "cc"); \
273 #define IRQ_RESTORE(x) \
276 "msr cpsr_c, %0\n\t" \
277 : : "r" (x) : "memory", "cc"); \
280 #define CPU_READ_FLAGS() \
285 : "=r" (sreg) : : "memory", "cc"); \
289 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
291 #if (CONFIG_KERN && CONFIG_KERN_PREEMPT)
292 EXTERN_C void asm_irq_switch_context(void);
295 * At the beginning of any ISR immediately ajust the
296 * return address and store all the caller-save
297 * registers (the ISR may change these registers that
298 * are shared with the user-context).
300 #define IRQ_ENTRY() asm volatile ( \
301 "sub lr, lr, #4\n\t" \
302 "stmfd sp!, {r0-r3, ip, lr}\n\t")
303 #define IRQ_EXIT() asm volatile ( \
304 "b asm_irq_switch_context\n\t")
306 * Function attribute to declare an interrupt service
309 * An ISR function must be declared as naked because we
310 * want to add our IRQ_ENTRY() prologue and IRQ_EXIT()
311 * epilogue code to handle the context switch and save
312 * all the registers (not only the callee-save).
315 #define ISR_FUNC __attribute__((naked))
318 * The compiler cannot establish which
319 * registers actually need to be saved, because
320 * the interrupt can happen at any time, so the
321 * "normal" prologue and epilogue used for a
322 * generic function call are not suitable for
325 * Using a naked function has the drawback that
326 * the stack is not automatically adjusted at
327 * this point, like a "normal" function call.
329 * So, an ISR can _only_ contain other function
330 * calls and they can't use the stack in any
333 * NOTE: we need to explicitly disable IRQs after
334 * IRQ_ENTRY(), because the IRQ status flag is not
335 * masked by the hardware and an IRQ ack inside the ISR
336 * may cause the triggering of another IRQ before
337 * exiting from the current ISR.
339 * The respective IRQ_ENABLE is not necessary, because
340 * IRQs will be automatically re-enabled when restoring
341 * the context of the user task.
343 #define DECLARE_ISR_CONTEXT_SWITCH(func) \
344 void ISR_FUNC func(void); \
345 static NOINLINE void __isr_##func(void); \
346 void ISR_FUNC func(void) \
353 static NOINLINE void __isr_##func(void)
355 * Interrupt service routine prototype: can be used for
356 * forward declarations.
358 #define ISR_PROTO_CONTEXT_SWITCH(func) \
359 void ISR_FUNC func(void)
361 * With task priorities enabled each ISR is used a point to
362 * check if we need to perform a context switch.
364 * Instead, without priorities a context switch can occur only
365 * when the running task expires its time quantum. In this last
366 * case, the context switch can only occur in the timer
367 * ISR, that must be always declared with the
368 * DECLARE_ISR_CONTEXT_SWITCH() macro.
371 #define DECLARE_ISR(func) \
372 DECLARE_ISR_CONTEXT_SWITCH(func)
374 #define ISR_PROTO(func) \
375 ISR_PROTO_CONTEXT_SWITCH(func)
376 #endif /* !CONFIG_KERN_PRI */
377 #endif /* CONFIG_KERN_PREEMPT */
380 #define ISR_FUNC __attribute__((naked))
383 #define DECLARE_ISR(func) \
384 void ISR_FUNC func(void); \
386 * FIXME: avoid the inlining of this function. \
388 * This is terribly inefficient, but it's a \
389 * reliable workaround to avoid gcc blowing \
390 * away the stack (see the bug below): \
392 * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=41999 \
394 static NOINLINE void __isr_##func(void); \
395 void ISR_FUNC func(void) \
398 "sub lr, lr, #4\n\t" \
399 "stmfd sp!, {r0-r3, ip, lr}\n\t"); \
402 "ldmfd sp!, {r0-r3, ip, pc}^\n\t"); \
404 static NOINLINE void __isr_##func(void)
406 #ifndef DECLARE_ISR_CONTEXT_SWITCH
407 #define DECLARE_ISR_CONTEXT_SWITCH(func) DECLARE_ISR(func)
410 #define ISR_PROTO(func) void ISR_FUNC func(void)
412 #ifndef ISR_PROTO_CONTEXT_SWITCH
413 #define ISR_PROTO_CONTEXT_SWITCH(func) ISR_PROTO(func)
416 #endif /* !__IAR_SYSTEMS_ICC_ */
420 /* Get IRQ_* definitions from the hosting environment. */
423 #define IRQ_DISABLE FIXME
424 #define IRQ_ENABLE FIXME
425 #define IRQ_SAVE_DISABLE(x) FIXME
426 #define IRQ_RESTORE(x) FIXME
427 #define IRQ_ENABLED() FIXME
428 #endif /* OS_EMBEDDED */
432 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
433 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
435 #define IRQ_SAVE_DISABLE(x) \
436 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
437 #define IRQ_RESTORE(x) \
438 do { (void)x; asm(move x,SR); } while (0)
440 static inline bool irq_running(void)
442 extern void *user_sp;
445 #define IRQ_RUNNING() irq_running()
447 static inline bool irq_enabled(void)
451 return !(x & 0x0200);
453 #define IRQ_ENABLED() irq_enabled()
457 #define IRQ_DISABLE asm volatile ("cli" ::)
458 #define IRQ_ENABLE asm volatile ("sei" ::)
460 #define IRQ_SAVE_DISABLE(x) \
462 __asm__ __volatile__( \
463 "in %0,__SREG__\n\t" \
465 : "=r" (x) : /* no inputs */ : "cc" \
469 #define IRQ_RESTORE(x) \
471 __asm__ __volatile__( \
472 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
476 #define IRQ_ENABLED() \
479 __asm__ __volatile__( \
480 "in %0,__SREG__\n\t" \
481 : "=r" (sreg) /* no inputs & no clobbers */ \
483 (bool)(sreg & 0x80); \
485 #if (CONFIG_KERN && CONFIG_KERN_PREEMPT)
486 #define DECLARE_ISR_CONTEXT_SWITCH(vect) \
487 INLINE void __isr_##vect(void); \
491 IRQ_PREEMPT_HANDLER(); \
493 INLINE void __isr_##vect(void)
496 * With task priorities enabled each ISR is used a point to
497 * check if we need to perform a context switch.
499 * Instead, without priorities a context switch can occur only
500 * when the running task expires its time quantum. In this last
501 * case, the context switch can only occur in the timer ISR,
502 * that must be always declared with the
503 * DECLARE_ISR_CONTEXT_SWITCH() macro.
506 #define DECLARE_ISR(func) \
507 DECLARE_ISR_CONTEXT_SWITCH(func)
509 * Interrupt service routine prototype: can be used for
510 * forward declarations.
512 #define ISR_PROTO(func) \
513 ISR_PROTO_CONTEXT_SWITCH(func)
514 #endif /* !CONFIG_KERN_PRI */
518 #define ISR_PROTO(vect) ISR(vect)
521 #define DECLARE_ISR(vect) ISR(vect)
523 #ifndef DECLARE_ISR_CONTEXT_SWITCH
524 #define DECLARE_ISR_CONTEXT_SWITCH(vect) ISR(vect)
526 #ifndef ISR_PROTO_CONTEXT_SWITCH
527 #define ISR_PROTO_CONTEXT_SWITCH(vect) ISR(vect)
532 /* Get the compiler defined macros */
534 #define IRQ_DISABLE dint()
535 #define IRQ_ENABLE eint()
538 #error No CPU_... defined.
542 /// Ensure callee is running within an interrupt
543 #define ASSERT_IRQ_CONTEXT() ASSERT(IRQ_RUNNING())
545 /// Ensure callee is not running within an interrupt
546 #define ASSERT_USER_CONTEXT() ASSERT(!IRQ_RUNNING())
548 #define IRQ_RUNNING() false
549 #define ASSERT_USER_CONTEXT() do {} while(0)
550 #define ASSERT_IRQ_CONTEXT() do {} while(0)
554 /// Ensure interrupts are enabled
555 #define IRQ_ASSERT_ENABLED() ASSERT(IRQ_ENABLED())
557 /// Ensure interrupts are not enabled
558 #define IRQ_ASSERT_DISABLED() ASSERT(!IRQ_ENABLED())
560 #define IRQ_ASSERT_ENABLED() do {} while(0)
561 #define IRQ_ASSERT_DISABLED() do {} while(0)
565 #ifndef IRQ_PREEMPT_HANDLER
566 #if (CONFIG_KERN && CONFIG_KERN_PREEMPT)
568 * Handle preemptive context switch inside timer IRQ.
570 INLINE void IRQ_PREEMPT_HANDLER(void)
572 if (proc_needPreempt())
576 #define IRQ_PREEMPT_HANDLER() /* Nothing */
581 * Execute \a CODE atomically with respect to interrupts.
583 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
585 #define ATOMIC(CODE) \
587 cpu_flags_t __flags; \
588 IRQ_SAVE_DISABLE(__flags); \
590 IRQ_RESTORE(__flags); \
593 #endif /* CPU_IRQ_H */