e27a77fe1021f215e2e44d11c2419b5fecfa26fb
[bertos.git] / bertos / cpu / irq.h
1 /**
2  * \file
3  * <!--
4  * This file is part of BeRTOS.
5  *
6  * Bertos is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  *
20  * As a special exception, you may use this file as part of a free software
21  * library without restriction.  Specifically, if other files instantiate
22  * templates or use macros or inline functions from this file, or you compile
23  * this file and link it with other files to produce an executable, this
24  * file does not by itself cause the resulting executable to be covered by
25  * the GNU General Public License.  This exception does not however
26  * invalidate any other reasons why the executable file might be covered by
27  * the GNU General Public License.
28  *
29  * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30  * Copyright 2004 Giovanni Bajo
31  *
32  * -->
33  *
34  * \brief CPU-specific IRQ definitions.
35  *
36  * \author Giovanni Bajo <rasky@develer.com>
37  * \author Bernie Innocenti <bernie@codewiz.org>
38  * \author Stefano Fedrigo <aleph@develer.com>
39  * \author Francesco Sacchi <batt@develer.com>
40  */
41 #ifndef CPU_IRQ_H
42 #define CPU_IRQ_H
43
44 #include "detect.h"
45 #include "types.h"
46
47 #include <kern/proc.h> /* proc_needPreempt() / proc_preempt() */
48
49 #include <cfg/compiler.h> /* for uintXX_t */
50 #include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */
51
52 #if CPU_I196
53         #define IRQ_DISABLE             disable_interrupt()
54         #define IRQ_ENABLE              enable_interrupt()
55 #elif CPU_X86
56
57         /* Get IRQ_* definitions from the hosting environment. */
58         #include <cfg/os.h>
59         #if OS_EMBEDDED
60                 #define IRQ_DISABLE             FIXME
61                 #define IRQ_ENABLE              FIXME
62                 #define IRQ_SAVE_DISABLE(x)     FIXME
63                 #define IRQ_RESTORE(x)          FIXME
64         #endif /* OS_EMBEDDED */
65
66 #elif CPU_CM3
67         /* Cortex-M3 */
68
69         /*
70          * Interrupt priority.
71          *
72          * NOTE: 0 means that an interrupt is not affected by the global IRQ
73          * priority settings.
74          */
75         #define IRQ_PRIO                0x80
76         #define IRQ_PRIO_MIN            0xf0
77         #define IRQ_PRIO_MAX            0
78         /*
79          * To disable interrupts we just raise the system base priority to a
80          * number lower than the default IRQ priority. In this way, all the
81          * "normal" interrupt can't be triggered. High-priority interrupt can
82          * still happen (at the moment only the soft-interrupt svcall uses a
83          * priority greater than the default IRQ priority).
84          *
85          * To enable interrupts we set the system base priority to 0, that
86          * means IRQ priority mechanism is disabled, and any interrupt can
87          * happen.
88          */
89         #define IRQ_PRIO_DISABLED       0x40
90         #define IRQ_PRIO_ENABLED        0
91
92         #define IRQ_DISABLE                                             \
93         ({                                                              \
94                 register cpu_flags_t reg = IRQ_PRIO_DISABLED;           \
95                 asm volatile (                                          \
96                         "msr basepri, %0"                               \
97                         : : "r"(reg) : "memory", "cc");                 \
98         })
99
100         #define IRQ_ENABLE                                              \
101         ({                                                              \
102                 register cpu_flags_t reg = IRQ_PRIO_ENABLED;            \
103                 asm volatile (                                          \
104                         "msr basepri, %0"                               \
105                         : : "r"(reg) : "memory", "cc");                 \
106         })
107
108         #define CPU_READ_FLAGS()                                        \
109         ({                                                              \
110                 register cpu_flags_t reg;                               \
111                 asm volatile (                                          \
112                         "mrs %0, basepri"                               \
113                          : "=r"(reg) : : "memory", "cc");               \
114                 reg;                                                    \
115         })
116
117         #define IRQ_SAVE_DISABLE(x)                                     \
118         ({                                                              \
119                 x = CPU_READ_FLAGS();                                   \
120                 IRQ_DISABLE;                                            \
121         })
122
123         #define IRQ_RESTORE(x)                                          \
124         ({                                                              \
125                 asm volatile (                                          \
126                         "msr basepri, %0"                               \
127                         : : "r"(x) : "memory", "cc");                   \
128         })
129
130         #define IRQ_ENABLED() (CPU_READ_FLAGS() == IRQ_PRIO_ENABLED)
131
132         INLINE bool irq_running(void)
133         {
134                 register uint32_t ret;
135
136                 /*
137                  * Check if the current stack pointer is the main stack or
138                  * process stack: we use the main stack only in Handler mode,
139                  * so this means we're running inside an ISR.
140                  */
141                 asm volatile (
142                         "mrs %0, msp\n\t"
143                         "cmp sp, %0\n\t"
144                         "ite ne\n\t"
145                         "movne %0, #0\n\t"
146                         "moveq %0, #1\n\t" : "=r"(ret) : : "cc");
147                 return ret;
148         }
149         #define IRQ_RUNNING() irq_running()
150
151         #if CONFIG_KERN_PREEMPT
152
153                 #define DECLARE_ISR_CONTEXT_SWITCH(func)                \
154                 INLINE void __isr_##func(void);                         \
155                 void func(void)                                         \
156                 {                                                       \
157                         __isr_##func();                                 \
158                         if (!proc_needPreempt())                        \
159                                 return;                                 \
160                         /*
161                          * Set a PendSV request.
162                          *
163                          * The preemption handler will be called immediately
164                          * after this ISR in tail-chaining mode (without the
165                          * overhead of hardware state saving and restoration
166                          * between interrupts).
167                          */                                             \
168                         HWREG(NVIC_INT_CTRL) = NVIC_INT_CTRL_PEND_SV;   \
169                 }                                                       \
170                 INLINE void __isr_##func(void)
171
172                 /**
173                  * With task priorities enabled each ISR is used a point to
174                  * check if we need to perform a context switch.
175                  *
176                  * Instead, without priorities a context switch can occur only
177                  * when the running task expires its time quantum. In this last
178                  * case, the context switch can only occur in the timer ISR,
179                  * that must be always declared with the
180                  * DECLARE_ISR_CONTEXT_SWITCH() macro.
181                  */
182                 #if CONFIG_KERN_PRI
183                         #define DECLARE_ISR(func) \
184                                 DECLARE_ISR_CONTEXT_SWITCH(func)
185                         /**
186                          * Interrupt service routine prototype: can be used for
187                          * forward declarations.
188                          */
189                         #define ISR_PROTO(func) \
190                                 ISR_PROTO_CONTEXT_SWITCH(func)
191                 #endif /* !CONFIG_KERN_PRI */
192         #endif
193
194         #ifndef ISR_PROTO
195                 #define ISR_PROTO(func) void func(void)
196         #endif
197         #ifndef DECLARE_ISR
198                 #define DECLARE_ISR(func) void func(void)
199         #endif
200         #ifndef DECLARE_ISR_CONTEXT_SWITCH
201                 #define DECLARE_ISR_CONTEXT_SWITCH(func) void func(void)
202         #endif
203         #ifndef ISR_PROTO_CONTEXT_SWITCH
204                 #define ISR_PROTO_CONTEXT_SWITCH(func) void func(void)
205         #endif
206
207 #elif CPU_ARM
208
209         #ifdef __IAR_SYSTEMS_ICC__
210
211                 #include <inarm.h>
212
213                 #if __CPU_MODE__ == 1 /* Thumb */
214                         /* Use stubs */
215                         extern cpu_flags_t get_CPSR(void);
216                         extern void set_CPSR(cpu_flags_t flags);
217                 #else
218                         #define get_CPSR __get_CPSR
219                         #define set_CPSR __set_CPSR
220                 #endif
221
222                 #define IRQ_DISABLE __disable_interrupt()
223                 #define IRQ_ENABLE  __enable_interrupt()
224
225                 #define IRQ_SAVE_DISABLE(x) \
226                 do { \
227                         (x) = get_CPSR(); \
228                         __disable_interrupt(); \
229                 } while (0)
230
231                 #define IRQ_RESTORE(x) \
232                 do { \
233                         set_CPSR(x); \
234                 } while (0)
235
236                 #define IRQ_ENABLED() \
237                         ((bool)(get_CPSR() & 0xb0))
238
239         #else /* !__IAR_SYSTEMS_ICC__ */
240
241                 #define IRQ_DISABLE \
242                 do { \
243                         asm volatile ( \
244                                 "mrs r0, cpsr\n\t" \
245                                 "orr r0, r0, #0xc0\n\t" \
246                                 "msr cpsr_c, r0" \
247                                 ::: "r0" \
248                         ); \
249                 } while (0)
250
251                 #define IRQ_ENABLE \
252                 do { \
253                         asm volatile ( \
254                                 "mrs r0, cpsr\n\t" \
255                                 "bic r0, r0, #0xc0\n\t" \
256                                 "msr cpsr_c, r0" \
257                                 ::: "r0" \
258                         ); \
259                 } while (0)
260
261                 #define IRQ_SAVE_DISABLE(x) \
262                 do { \
263                         asm volatile ( \
264                                 "mrs %0, cpsr\n\t" \
265                                 "orr r0, %0, #0xc0\n\t" \
266                                 "msr cpsr_c, r0" \
267                                 : "=r" (x) \
268                                 : /* no inputs */ \
269                                 : "r0" \
270                         ); \
271                 } while (0)
272
273                 #define IRQ_RESTORE(x) \
274                 do { \
275                         asm volatile ( \
276                                 "msr cpsr_c, %0" \
277                                 : /* no outputs */ \
278                                 : "r" (x) \
279                         ); \
280                 } while (0)
281
282                 #define CPU_READ_FLAGS() \
283                 ({ \
284                         cpu_flags_t sreg; \
285                         asm volatile ( \
286                                 "mrs %0, cpsr\n\t" \
287                                 : "=r" (sreg) \
288                                 : /* no inputs */ \
289                         ); \
290                         sreg; \
291                 })
292
293                 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
294
295                 #if CONFIG_KERN_PREEMPT
296                         EXTERN_C void asm_irq_switch_context(void);
297
298                         /**
299                          * At the beginning of any ISR immediately ajust the
300                          * return address and store all the caller-save
301                          * registers (the ISR may change these registers that
302                          * are shared with the user-context).
303                          */
304                         #define IRQ_ENTRY() asm volatile ( \
305                                                 "sub    lr, lr, #4\n\t" \
306                                                 "stmfd  sp!, {r0-r3, ip, lr}\n\t")
307                         #define IRQ_EXIT()  asm volatile ( \
308                                                 "b      asm_irq_switch_context\n\t")
309                         /**
310                          * Function attribute to declare an interrupt service
311                          * routine.
312                          *
313                          * An ISR function must be declared as naked because we
314                          * want to add our IRQ_ENTRY() prologue and IRQ_EXIT()
315                          * epilogue code to handle the context switch and save
316                          * all the registers (not only the callee-save).
317                          *
318                          */
319                         #define ISR_FUNC __attribute__((naked))
320
321                         /**
322                          * The compiler cannot establish which
323                          * registers actually need to be saved, because
324                          * the interrupt can happen at any time, so the
325                          * "normal" prologue and epilogue used for a
326                          * generic function call are not suitable for
327                          * the ISR.
328                          *
329                          * Using a naked function has the drawback that
330                          * the stack is not automatically adjusted at
331                          * this point, like a "normal" function call.
332                          *
333                          * So, an ISR can _only_ contain other function
334                          * calls and they can't use the stack in any
335                          * other way.
336                          *
337                          * NOTE: we need to explicitly disable IRQs after
338                          * IRQ_ENTRY(), because the IRQ status flag is not
339                          * masked by the hardware and an IRQ ack inside the ISR
340                          * may cause the triggering of another IRQ before
341                          * exiting from the current ISR.
342                          *
343                          * The respective IRQ_ENABLE is not necessary, because
344                          * IRQs will be automatically re-enabled when restoring
345                          * the context of the user task.
346                          */
347                         #define DECLARE_ISR_CONTEXT_SWITCH(func)        \
348                                 void ISR_FUNC func(void);               \
349                                 static void __isr_##func(void);         \
350                                 void ISR_FUNC func(void)                \
351                                 {                                       \
352                                         IRQ_ENTRY();                    \
353                                         IRQ_DISABLE;                    \
354                                         __isr_##func();                 \
355                                         IRQ_EXIT();                     \
356                                 }                                       \
357                                 static void __isr_##func(void)
358                         /**
359                          * Interrupt service routine prototype: can be used for
360                          * forward declarations.
361                          */
362                         #define ISR_PROTO_CONTEXT_SWITCH(func)  \
363                                 void ISR_FUNC func(void)
364                         /**
365                          * With task priorities enabled each ISR is used a point to
366                          * check if we need to perform a context switch.
367                          *
368                          * Instead, without priorities a context switch can occur only
369                          * when the running task expires its time quantum. In this last
370                          * case, the context switch can only occur in the timer
371                          * ISR, that must be always declared with the
372                          * DECLARE_ISR_CONTEXT_SWITCH() macro.
373                          */
374                         #if CONFIG_KERN_PRI
375                                 #define DECLARE_ISR(func) \
376                                         DECLARE_ISR_CONTEXT_SWITCH(func)
377
378                                 #define ISR_PROTO(func) \
379                                         ISR_PROTO_CONTEXT_SWITCH(func)
380                         #endif /* !CONFIG_KERN_PRI */
381                 #endif /* CONFIG_KERN_PREEMPT */
382
383                 #ifndef DECLARE_ISR
384                         #define DECLARE_ISR(func) \
385                                 void __attribute__((interrupt)) func(void)
386                 #endif
387                 #ifndef DECLARE_ISR_CONTEXT_SWITCH
388                         #define DECLARE_ISR_CONTEXT_SWITCH(func) \
389                                 void __attribute__((interrupt)) func(void)
390                 #endif
391                 #ifndef ISR_PROTO
392                         #define ISR_PROTO(func) \
393                                 void __attribute__((interrupt)) func(void)
394                 #endif
395                 #ifndef ISR_PROTO_CONTEXT_SWITCH
396                         #define ISR_PROTO_CONTEXT_SWITCH(func)  \
397                                 void __attribute__((interrupt)) func(void)
398                 #endif
399
400         #endif /* !__IAR_SYSTEMS_ICC_ */
401
402 #elif CPU_PPC
403
404         /* Get IRQ_* definitions from the hosting environment. */
405         #include <cfg/os.h>
406         #if OS_EMBEDDED
407                 #define IRQ_DISABLE         FIXME
408                 #define IRQ_ENABLE          FIXME
409                 #define IRQ_SAVE_DISABLE(x) FIXME
410                 #define IRQ_RESTORE(x)      FIXME
411                 #define IRQ_ENABLED()       FIXME
412         #endif /* OS_EMBEDDED */
413
414 #elif CPU_DSP56K
415
416         #define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
417         #define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
418
419         #define IRQ_SAVE_DISABLE(x)  \
420                 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
421         #define IRQ_RESTORE(x)  \
422                 do { (void)x; asm(move x,SR); } while (0)
423
424         static inline bool irq_running(void)
425         {
426                 extern void *user_sp;
427                 return !!user_sp;
428         }
429         #define IRQ_RUNNING() irq_running()
430
431         static inline bool irq_enabled(void)
432         {
433                 uint16_t x;
434                 asm(move SR,x);
435                 return !(x & 0x0200);
436         }
437         #define IRQ_ENABLED() irq_enabled()
438
439 #elif CPU_AVR
440
441         #define IRQ_DISABLE   asm volatile ("cli" ::)
442         #define IRQ_ENABLE    asm volatile ("sei" ::)
443
444         #define IRQ_SAVE_DISABLE(x) \
445         do { \
446                 __asm__ __volatile__( \
447                         "in %0,__SREG__\n\t" \
448                         "cli" \
449                         : "=r" (x) : /* no inputs */ : "cc" \
450                 ); \
451         } while (0)
452
453         #define IRQ_RESTORE(x) \
454         do { \
455                 __asm__ __volatile__( \
456                         "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
457                 ); \
458         } while (0)
459
460         #define IRQ_ENABLED() \
461         ({ \
462                 uint8_t sreg; \
463                 __asm__ __volatile__( \
464                         "in %0,__SREG__\n\t" \
465                         : "=r" (sreg)  /* no inputs & no clobbers */ \
466                 ); \
467                 (bool)(sreg & 0x80); \
468         })
469         #if CONFIG_KERN_PREEMPT
470                 #define DECLARE_ISR_CONTEXT_SWITCH(vect)                \
471                         INLINE void __isr_##vect(void);                 \
472                         ISR(vect)                                       \
473                         {                                               \
474                                 __isr_##vect();                         \
475                                 IRQ_PREEMPT_HANDLER();                  \
476                         }                                               \
477                         INLINE void __isr_##vect(void)
478
479                 /**
480                  * With task priorities enabled each ISR is used a point to
481                  * check if we need to perform a context switch.
482                  *
483                  * Instead, without priorities a context switch can occur only
484                  * when the running task expires its time quantum. In this last
485                  * case, the context switch can only occur in the timer ISR,
486                  * that must be always declared with the
487                  * DECLARE_ISR_CONTEXT_SWITCH() macro.
488                  */
489                 #if CONFIG_KERN_PRI
490                         #define DECLARE_ISR(func) \
491                                 DECLARE_ISR_CONTEXT_SWITCH(func)
492                         /**
493                          * Interrupt service routine prototype: can be used for
494                          * forward declarations.
495                          */
496                         #define ISR_PROTO(func) \
497                                 ISR_PROTO_CONTEXT_SWITCH(func)
498                 #endif /* !CONFIG_KERN_PRI */
499         #endif
500
501         #ifndef ISR_PROTO
502                 #define ISR_PROTO(vect) ISR(vect)
503         #endif
504         #ifndef DECLARE_ISR
505                 #define DECLARE_ISR(vect) ISR(vect)
506         #endif
507         #ifndef DECLARE_ISR_CONTEXT_SWITCH
508                 #define DECLARE_ISR_CONTEXT_SWITCH(vect) ISR(vect)
509         #endif
510         #ifndef ISR_PROTO_CONTEXT_SWITCH
511                 #define ISR_PROTO_CONTEXT_SWITCH(vect) ISR(vect)
512         #endif
513
514 #else
515         #error No CPU_... defined.
516 #endif
517
518 #ifdef IRQ_RUNNING
519         /// Ensure callee is running within an interrupt
520         #define ASSERT_IRQ_CONTEXT()  ASSERT(IRQ_RUNNING())
521
522         /// Ensure callee is not running within an interrupt
523         #define ASSERT_USER_CONTEXT() ASSERT(!IRQ_RUNNING())
524 #else
525         #define IRQ_RUNNING()   false
526         #define ASSERT_USER_CONTEXT()  do {} while(0)
527         #define ASSERT_IRQ_CONTEXT()   do {} while(0)
528 #endif
529
530 #ifdef IRQ_ENABLED
531         /// Ensure interrupts are enabled
532         #define IRQ_ASSERT_ENABLED()  ASSERT(IRQ_ENABLED())
533
534         /// Ensure interrupts are not enabled
535         #define IRQ_ASSERT_DISABLED() ASSERT(!IRQ_ENABLED())
536 #else
537         #define IRQ_ASSERT_ENABLED() do {} while(0)
538         #define IRQ_ASSERT_DISABLED() do {} while(0)
539 #endif
540
541
542 #ifndef IRQ_PREEMPT_HANDLER
543         #if CONFIG_KERN_PREEMPT
544                 /**
545                  * Handle preemptive context switch inside timer IRQ.
546                  */
547                 INLINE void IRQ_PREEMPT_HANDLER(void)
548                 {
549                         if (proc_needPreempt())
550                                 proc_preempt();
551                 }
552         #else
553                 #define IRQ_PREEMPT_HANDLER() /* Nothing */
554         #endif
555 #endif
556
557 /**
558  * Execute \a CODE atomically with respect to interrupts.
559  *
560  * \see IRQ_SAVE_DISABLE IRQ_RESTORE
561  */
562 #define ATOMIC(CODE) \
563         do { \
564                 cpu_flags_t __flags; \
565                 IRQ_SAVE_DISABLE(__flags); \
566                 CODE; \
567                 IRQ_RESTORE(__flags); \
568         } while (0)
569
570 #endif /* CPU_IRQ_H */