4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific IRQ definitions.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernie Innocenti <bernie@codewiz.org>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
47 #include <kern/proc.h> /* proc_needPreempt() / proc_preempt() */
49 #include <cfg/compiler.h> /* for uintXX_t */
50 #include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */
53 #define IRQ_DISABLE disable_interrupt()
54 #define IRQ_ENABLE enable_interrupt()
57 /* Get IRQ_* definitions from the hosting environment. */
60 #define IRQ_DISABLE FIXME
61 #define IRQ_ENABLE FIXME
62 #define IRQ_SAVE_DISABLE(x) FIXME
63 #define IRQ_RESTORE(x) FIXME
64 #endif /* OS_EMBEDDED */
72 * NOTE: 0 means that an interrupt is not affected by the global IRQ
76 #define IRQ_PRIO_MIN 0xf0
77 #define IRQ_PRIO_MAX 0
79 * To disable interrupts we just raise the system base priority to a
80 * number lower than the default IRQ priority. In this way, all the
81 * "normal" interrupt can't be triggered. High-priority interrupt can
82 * still happen (at the moment only the soft-interrupt svcall uses a
83 * priority greater than the default IRQ priority).
85 * To enable interrupts we set the system base priority to 0, that
86 * means IRQ priority mechanism is disabled, and any interrupt can
89 #define IRQ_PRIO_DISABLED 0x40
90 #define IRQ_PRIO_ENABLED 0
94 register cpu_flags_t reg = IRQ_PRIO_DISABLED; \
97 : : "r"(reg) : "memory", "cc"); \
102 register cpu_flags_t reg = IRQ_PRIO_ENABLED; \
105 : : "r"(reg) : "memory", "cc"); \
108 #define CPU_READ_FLAGS() \
110 register cpu_flags_t reg; \
113 : "=r"(reg) : : "memory", "cc"); \
117 #define IRQ_SAVE_DISABLE(x) \
119 x = CPU_READ_FLAGS(); \
123 #define IRQ_RESTORE(x) \
127 : : "r"(x) : "memory", "cc"); \
130 #define IRQ_ENABLED() (CPU_READ_FLAGS() == IRQ_PRIO_ENABLED)
132 INLINE bool irq_running(void)
134 register uint32_t ret;
137 * Check if the current stack pointer is the main stack or
138 * process stack: we use the main stack only in Handler mode,
139 * so this means we're running inside an ISR.
146 "moveq %0, #1\n\t" : "=r"(ret) : : "cc");
149 #define IRQ_RUNNING() irq_running()
151 #if CONFIG_KERN_PREEMPT
153 #define DECLARE_ISR_CONTEXT_SWITCH(func) \
154 INLINE void __isr_##func(void); \
158 if (!proc_needPreempt()) \
161 * Set a PendSV request.
163 * The preemption handler will be called immediately
164 * after this ISR in tail-chaining mode (without the
165 * overhead of hardware state saving and restoration
166 * between interrupts).
168 HWREG(NVIC_INT_CTRL) = NVIC_INT_CTRL_PEND_SV; \
170 INLINE void __isr_##func(void)
173 * With task priorities enabled each ISR is used a point to
174 * check if we need to perform a context switch.
176 * Instead, without priorities a context switch can occur only
177 * when the running task expires its time quantum. In this last
178 * case, the context switch can only occur in the timer ISR,
179 * that must be always declared with the
180 * DECLARE_ISR_CONTEXT_SWITCH() macro.
183 #define DECLARE_ISR(func) \
184 DECLARE_ISR_CONTEXT_SWITCH(func)
186 * Interrupt service routine prototype: can be used for
187 * forward declarations.
189 #define ISR_PROTO(func) \
190 ISR_PROTO_CONTEXT_SWITCH(func)
191 #endif /* !CONFIG_KERN_PRI */
195 #define ISR_PROTO(func) void func(void)
198 #define DECLARE_ISR(func) void func(void)
200 #ifndef DECLARE_ISR_CONTEXT_SWITCH
201 #define DECLARE_ISR_CONTEXT_SWITCH(func) void func(void)
203 #ifndef ISR_PROTO_CONTEXT_SWITCH
204 #define ISR_PROTO_CONTEXT_SWITCH(func) void func(void)
209 #ifdef __IAR_SYSTEMS_ICC__
213 #if __CPU_MODE__ == 1 /* Thumb */
215 extern cpu_flags_t get_CPSR(void);
216 extern void set_CPSR(cpu_flags_t flags);
218 #define get_CPSR __get_CPSR
219 #define set_CPSR __set_CPSR
222 #define IRQ_DISABLE __disable_interrupt()
223 #define IRQ_ENABLE __enable_interrupt()
225 #define IRQ_SAVE_DISABLE(x) \
228 __disable_interrupt(); \
231 #define IRQ_RESTORE(x) \
236 #define IRQ_ENABLED() \
237 ((bool)(get_CPSR() & 0xb0))
239 #else /* !__IAR_SYSTEMS_ICC__ */
241 #define IRQ_DISABLE \
245 "orr r0, r0, #0xc0\n\t" \
255 "bic r0, r0, #0xc0\n\t" \
261 #define IRQ_SAVE_DISABLE(x) \
265 "orr r0, %0, #0xc0\n\t" \
273 #define IRQ_RESTORE(x) \
282 #define CPU_READ_FLAGS() \
293 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
295 #if CONFIG_KERN_PREEMPT
296 EXTERN_C void asm_irq_switch_context(void);
299 * At the beginning of any ISR immediately ajust the
300 * return address and store all the caller-save
301 * registers (the ISR may change these registers that
302 * are shared with the user-context).
304 #define IRQ_ENTRY() asm volatile ( \
305 "sub lr, lr, #4\n\t" \
306 "stmfd sp!, {r0-r3, ip, lr}\n\t")
307 #define IRQ_EXIT() asm volatile ( \
308 "b asm_irq_switch_context\n\t")
310 * Function attribute to declare an interrupt service
313 * An ISR function must be declared as naked because we
314 * want to add our IRQ_ENTRY() prologue and IRQ_EXIT()
315 * epilogue code to handle the context switch and save
316 * all the registers (not only the callee-save).
319 #define ISR_FUNC __attribute__((naked))
322 * The compiler cannot establish which
323 * registers actually need to be saved, because
324 * the interrupt can happen at any time, so the
325 * "normal" prologue and epilogue used for a
326 * generic function call are not suitable for
329 * Using a naked function has the drawback that
330 * the stack is not automatically adjusted at
331 * this point, like a "normal" function call.
333 * So, an ISR can _only_ contain other function
334 * calls and they can't use the stack in any
337 * NOTE: we need to explicitly disable IRQs after
338 * IRQ_ENTRY(), because the IRQ status flag is not
339 * masked by the hardware and an IRQ ack inside the ISR
340 * may cause the triggering of another IRQ before
341 * exiting from the current ISR.
343 * The respective IRQ_ENABLE is not necessary, because
344 * IRQs will be automatically re-enabled when restoring
345 * the context of the user task.
347 #define DECLARE_ISR_CONTEXT_SWITCH(func) \
348 void ISR_FUNC func(void); \
349 static void __isr_##func(void); \
350 void ISR_FUNC func(void) \
357 static void __isr_##func(void)
359 * Interrupt service routine prototype: can be used for
360 * forward declarations.
362 #define ISR_PROTO_CONTEXT_SWITCH(func) \
363 void ISR_FUNC func(void)
365 * With task priorities enabled each ISR is used a point to
366 * check if we need to perform a context switch.
368 * Instead, without priorities a context switch can occur only
369 * when the running task expires its time quantum. In this last
370 * case, the context switch can only occur in the timer
371 * ISR, that must be always declared with the
372 * DECLARE_ISR_CONTEXT_SWITCH() macro.
375 #define DECLARE_ISR(func) \
376 DECLARE_ISR_CONTEXT_SWITCH(func)
378 #define ISR_PROTO(func) \
379 ISR_PROTO_CONTEXT_SWITCH(func)
380 #endif /* !CONFIG_KERN_PRI */
381 #endif /* CONFIG_KERN_PREEMPT */
384 #define DECLARE_ISR(func) \
385 void __attribute__((interrupt)) func(void)
387 #ifndef DECLARE_ISR_CONTEXT_SWITCH
388 #define DECLARE_ISR_CONTEXT_SWITCH(func) \
389 void __attribute__((interrupt)) func(void)
392 #define ISR_PROTO(func) \
393 void __attribute__((interrupt)) func(void)
395 #ifndef ISR_PROTO_CONTEXT_SWITCH
396 #define ISR_PROTO_CONTEXT_SWITCH(func) \
397 void __attribute__((interrupt)) func(void)
400 #endif /* !__IAR_SYSTEMS_ICC_ */
404 /* Get IRQ_* definitions from the hosting environment. */
407 #define IRQ_DISABLE FIXME
408 #define IRQ_ENABLE FIXME
409 #define IRQ_SAVE_DISABLE(x) FIXME
410 #define IRQ_RESTORE(x) FIXME
411 #define IRQ_ENABLED() FIXME
412 #endif /* OS_EMBEDDED */
416 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
417 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
419 #define IRQ_SAVE_DISABLE(x) \
420 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
421 #define IRQ_RESTORE(x) \
422 do { (void)x; asm(move x,SR); } while (0)
424 static inline bool irq_running(void)
426 extern void *user_sp;
429 #define IRQ_RUNNING() irq_running()
431 static inline bool irq_enabled(void)
435 return !(x & 0x0200);
437 #define IRQ_ENABLED() irq_enabled()
441 #define IRQ_DISABLE asm volatile ("cli" ::)
442 #define IRQ_ENABLE asm volatile ("sei" ::)
444 #define IRQ_SAVE_DISABLE(x) \
446 __asm__ __volatile__( \
447 "in %0,__SREG__\n\t" \
449 : "=r" (x) : /* no inputs */ : "cc" \
453 #define IRQ_RESTORE(x) \
455 __asm__ __volatile__( \
456 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
460 #define IRQ_ENABLED() \
463 __asm__ __volatile__( \
464 "in %0,__SREG__\n\t" \
465 : "=r" (sreg) /* no inputs & no clobbers */ \
467 (bool)(sreg & 0x80); \
469 #if CONFIG_KERN_PREEMPT
470 #define DECLARE_ISR_CONTEXT_SWITCH(vect) \
471 INLINE void __isr_##vect(void); \
475 IRQ_PREEMPT_HANDLER(); \
477 INLINE void __isr_##vect(void)
480 * With task priorities enabled each ISR is used a point to
481 * check if we need to perform a context switch.
483 * Instead, without priorities a context switch can occur only
484 * when the running task expires its time quantum. In this last
485 * case, the context switch can only occur in the timer ISR,
486 * that must be always declared with the
487 * DECLARE_ISR_CONTEXT_SWITCH() macro.
490 #define DECLARE_ISR(func) \
491 DECLARE_ISR_CONTEXT_SWITCH(func)
493 * Interrupt service routine prototype: can be used for
494 * forward declarations.
496 #define ISR_PROTO(func) \
497 ISR_PROTO_CONTEXT_SWITCH(func)
498 #endif /* !CONFIG_KERN_PRI */
502 #define ISR_PROTO(vect) ISR(vect)
505 #define DECLARE_ISR(vect) ISR(vect)
507 #ifndef DECLARE_ISR_CONTEXT_SWITCH
508 #define DECLARE_ISR_CONTEXT_SWITCH(vect) ISR(vect)
510 #ifndef ISR_PROTO_CONTEXT_SWITCH
511 #define ISR_PROTO_CONTEXT_SWITCH(vect) ISR(vect)
515 #error No CPU_... defined.
519 /// Ensure callee is running within an interrupt
520 #define ASSERT_IRQ_CONTEXT() ASSERT(IRQ_RUNNING())
522 /// Ensure callee is not running within an interrupt
523 #define ASSERT_USER_CONTEXT() ASSERT(!IRQ_RUNNING())
525 #define IRQ_RUNNING() false
526 #define ASSERT_USER_CONTEXT() do {} while(0)
527 #define ASSERT_IRQ_CONTEXT() do {} while(0)
531 /// Ensure interrupts are enabled
532 #define IRQ_ASSERT_ENABLED() ASSERT(IRQ_ENABLED())
534 /// Ensure interrupts are not enabled
535 #define IRQ_ASSERT_DISABLED() ASSERT(!IRQ_ENABLED())
537 #define IRQ_ASSERT_ENABLED() do {} while(0)
538 #define IRQ_ASSERT_DISABLED() do {} while(0)
542 #ifndef IRQ_PREEMPT_HANDLER
543 #if CONFIG_KERN_PREEMPT
545 * Handle preemptive context switch inside timer IRQ.
547 INLINE void IRQ_PREEMPT_HANDLER(void)
549 if (proc_needPreempt())
553 #define IRQ_PREEMPT_HANDLER() /* Nothing */
558 * Execute \a CODE atomically with respect to interrupts.
560 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
562 #define ATOMIC(CODE) \
564 cpu_flags_t __flags; \
565 IRQ_SAVE_DISABLE(__flags); \
567 IRQ_RESTORE(__flags); \
570 #endif /* CPU_IRQ_H */