4 * This file is part of BeRTOS.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2010 Mohamed <mtarek16@gmail.com>
34 * \brief MSP430 debug support (implementation).
36 * \author Mohamed Tarek <mtarek16@gmail.com>
39 #include "kdebug_msp430.h" /* for UART clock source definitions */
41 #include "hw/hw_ser.h" /* bus macros overrides */
42 #include "cfg/cfg_debug.h"
44 #include <cfg/macros.h> /* for DIV_ROUND */
46 #include <cpu/types.h>
51 #if CONFIG_KDEBUG_PORT == 0
53 #ifndef KDBG_UART0_BUS_INIT
54 #define KDBG_UART0_BUS_INIT do {} while (0)
56 #ifndef KDBG_UART0_BUS_RX
57 #define KDBG_UART0_BUS_RX do {} while (0)
59 #ifndef KDBG_UART0_BUS_TX
60 #define KDBG_UART0_BUS_TX do {} while (0)
63 /* USCI Register definitions */
64 #define UCSTAT UCA0STAT
65 #define UCTXBUF UCA0TXBUF
66 #define UCRXBUF UCA0RXBUF
67 #define UCTXIFG UCA0TXIFG
68 #define UCRXIFG UCA0RXIFG
69 #define UCTXIE UCA0TXIE
70 #define UCRXIE UCA0RXIE
71 #define UCCTL0 UCA0CTL0
72 #define UCCTL1 UCA0CTL1
75 #define UCMCTL UCA0MCTL
80 #define KDBG_MSP430_UART_PINS_INIT() do{ P3SEL = 0x30; }while(0)
86 #error only 1 UART availbale, CONFIG_KDEBUG_PORT should be 0
91 #define KDBG_WAIT_READY() do { while((UCSTAT & UCBUSY)); } while(0)
92 #define KDBG_WAIT_TXDONE() do { while(!(IFG & UCTXIFG)); } while(0)
94 #define KDBG_WRITE_CHAR(c) do { UCTXBUF = (c); } while(0)
96 #define KDBG_MASK_IRQ(old) do { \
98 IE &= ~(UCTXIE|UCRXIE);\
101 #define KDBG_RESTORE_IRQ(old) do { \
102 KDBG_WAIT_TXDONE(); \
106 #if CONFIG_KDEBUG_CLOCK_FREQ
107 #define KDBG_MSP430_FREQ CONFIG_KDEBUG_CLOCK_FREQ
109 #define KDBG_MSP430_FREQ CPU_FREQ
112 typedef uint8_t kdbg_irqsave_t;
114 INLINE void kdbg_hw_init(void)
116 /* Compute the clock prescaler for the desired baudrate */
117 uint16_t quot = DIV_ROUND(KDBG_MSP430_FREQ, CONFIG_KDEBUG_BAUDRATE);
118 KDBG_MSP430_UART_PINS_INIT(); // Configure USCI TX/RX pins
120 #if (CONFIG_KDEBUG_CLOCK_SOURCE == KDBG_UART_SMCLK)
121 UCCTL1 |= UCSSEL_SMCLK;
123 UCCTL1 |= UCSSEL_ACLK;
126 UCBR0 = quot & 0xFF; // Setup clock prescaler for the UART
129 UCMCTL = UCBRS0; // No Modulation
130 UCCTL0 = 0; // Default UART settings (8N1)
131 UCCTL1 &= ~UCSWRST; // Initialize USCI state machine
132 KDBG_MASK_IRQ(IE2); // Disable USCI interrupts