4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2010 Mohamed <mtarek16@gmail.com>
34 * \brief MSP430 debug support (implementation).
36 * \author Mohamed Tarek <mtarek16@gmail.com>
39 #include <hw/hw_cpufreq.h> /* for CPU_FREQ */
40 #include "hw/hw_ser.h" /* bus macros overrides */
42 #include "cfg/cfg_debug.h"
43 #include <cfg/macros.h> /* for DIV_ROUND */
45 #include <cpu/types.h>
50 #if CONFIG_KDEBUG_PORT == 0
52 #ifndef KDBG_UART0_BUS_INIT
53 #define KDBG_UART0_BUS_INIT do {} while (0)
55 #ifndef KDBG_UART0_BUS_RX
56 #define KDBG_UART0_BUS_RX do {} while (0)
58 #ifndef KDBG_UART0_BUS_TX
59 #define KDBG_UART0_BUS_TX do {} while (0)
62 /* USCI Register definitions */
63 #define UCSTAT UCA0STAT
64 #define UCTXBUF UCA0TXBUF
65 #define UCRXBUF UCA0RXBUF
66 #define UCTXIFG UCA0TXIFG
67 #define UCRXIFG UCA0RXIFG
68 #define UCTXIE UCA0TXIE
69 #define UCRXIE UCA0RXIE
70 #define UCCTL0 UCA0CTL0
71 #define UCCTL1 UCA0CTL1
74 #define UCMCTL UCA0MCTL
79 #define KDBG_MSP430_UART_PINS_INIT() do{ P3SEL = 0x30; }while(0)
85 #error only 1 UART availbale, CONFIG_KDEBUG_PORT should be 0
90 #define KDBG_WAIT_READY() do { while((UCSTAT & UCBUSY)); } while(0)
91 #define KDBG_WAIT_TXDONE() do { while(!(IFG & UCTXIFG)); } while(0)
93 #define KDBG_WRITE_CHAR(c) do { UCTXBUF = (c); } while(0)
95 #define KDBG_MASK_IRQ(old) do { \
97 IE &= ~(UCTXIE|UCRXIE);\
100 #define KDBG_RESTORE_IRQ(old) do { \
101 KDBG_WAIT_TXDONE(); \
105 typedef uint8_t kdbg_irqsave_t;
107 INLINE void kdbg_hw_init(void)
109 /* Assume SMCLK = MCLK = DCO = CPU_FREQ */
110 /* Compute the baud rate */
111 uint16_t quot = DIV_ROUND(CPU_FREQ, CONFIG_KDEBUG_BAUDRATE);
112 KDBG_MSP430_UART_PINS_INIT(); // Configure USCI TX/RX pins
113 UCCTL1 |= UCSSEL_2; // use SMCLK
116 UCMCTL = UCBRS0; // No Modulation
117 UCCTL0 = 0; // Default UART settings (8N1)
118 UCCTL1 &= ~UCSWRST; // Initialize USCI state machine
119 KDBG_MASK_IRQ(IE2); // Disable USCI interrupts