4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
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29 * Copyright 2003, 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2010 Mohamed <mtarek16@gmail.com>
34 * \brief MSP430 debug support (implementation).
36 * \author Mohamed Tarek <mtarek16@gmail.com>
39 #include <hw/hw_cpufreq.h> /* for CPU_FREQ */
40 #include "hw/hw_ser.h" /* bus macros overrides */
42 #include "cfg/cfg_debug.h"
43 #include <cfg/macros.h> /* for DIV_ROUND */
45 #include "kdebug_msp430.h" /* for UART clock source definitions */
47 #include <cpu/types.h>
52 #if CONFIG_KDEBUG_PORT == 0
54 #ifndef KDBG_UART0_BUS_INIT
55 #define KDBG_UART0_BUS_INIT do {} while (0)
57 #ifndef KDBG_UART0_BUS_RX
58 #define KDBG_UART0_BUS_RX do {} while (0)
60 #ifndef KDBG_UART0_BUS_TX
61 #define KDBG_UART0_BUS_TX do {} while (0)
64 /* USCI Register definitions */
65 #define UCSTAT UCA0STAT
66 #define UCTXBUF UCA0TXBUF
67 #define UCRXBUF UCA0RXBUF
68 #define UCTXIFG UCA0TXIFG
69 #define UCRXIFG UCA0RXIFG
70 #define UCTXIE UCA0TXIE
71 #define UCRXIE UCA0RXIE
72 #define UCCTL0 UCA0CTL0
73 #define UCCTL1 UCA0CTL1
76 #define UCMCTL UCA0MCTL
81 #define KDBG_MSP430_UART_PINS_INIT() do{ P3SEL = 0x30; }while(0)
87 #error only 1 UART availbale, CONFIG_KDEBUG_PORT should be 0
92 #define KDBG_WAIT_READY() do { while((UCSTAT & UCBUSY)); } while(0)
93 #define KDBG_WAIT_TXDONE() do { while(!(IFG & UCTXIFG)); } while(0)
95 #define KDBG_WRITE_CHAR(c) do { UCTXBUF = (c); } while(0)
97 #define KDBG_MASK_IRQ(old) do { \
99 IE &= ~(UCTXIE|UCRXIE);\
102 #define KDBG_RESTORE_IRQ(old) do { \
103 KDBG_WAIT_TXDONE(); \
107 #if CONFIG_KDEBUG_CLOCK_FREQ
108 #define KDBG_MSP430_FREQ CONFIG_KDEBUG_CLOCK_FREQ
110 #define KDBG_MSP430_FREQ CPU_FREQ
113 typedef uint8_t kdbg_irqsave_t;
115 INLINE void kdbg_hw_init(void)
117 /* Compute the clock prescaler for the desired baudrate */
118 uint16_t quot = DIV_ROUND(KDBG_MSP430_FREQ, CONFIG_KDEBUG_BAUDRATE);
119 KDBG_MSP430_UART_PINS_INIT(); // Configure USCI TX/RX pins
121 #if (CONFIG_KDEBUG_CLOCK_SOURCE == KDBG_UART_SMCLK)
122 UCCTL1 |= UCSSEL_SMCLK;
124 UCCTL1 |= UCSSEL_ACLK;
127 UCBR0 = quot & 0xFF; // Setup clock prescaler for the UART
130 UCMCTL = UCBRS0; // No Modulation
131 UCCTL0 = 0; // Default UART settings (8N1)
132 UCCTL1 &= ~UCSWRST; // Initialize USCI state machine
133 KDBG_MASK_IRQ(IE2); // Disable USCI interrupts