4 * This file is part of BeRTOS.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \defgroup i2s Generic I2S driver
38 * <b>Configuration file</b>: cfg_i2s.h
40 * \author Daniele Basile <asterix@develer.com>
42 * $WIZ$ module_name = "i2s"
43 * $WIZ$ module_configuration = "bertos/cfg/cfg_i2s.h"
44 * $WIZ$ module_supports = "not all"
51 #warning __FILTER_NEXT_WARNING__
52 #warning This API is ALPHA! we could change it..
54 #include <cfg/compiler.h>
55 #include <cfg/debug.h>
56 #include <cfg/macros.h>
60 #include CPU_HEADER(i2s)
65 typedef int (*i2s_write_t) (struct I2s *i2s, uint32_t sample);
66 typedef uint32_t (*i2s_read_t) (struct I2s *i2s);
67 typedef void (*i2s_dma_tx_buf_t) (struct I2s *i2s, void *buf, size_t len);
68 typedef void (*i2s_dma_rx_buf_t) (struct I2s *i2s, void *buf, size_t len);
69 typedef bool (*i2s_dma_tx_is_finished_t) (struct I2s *i2s);
70 typedef bool (*i2s_dma_rx_is_finished_t) (struct I2s *i2s);
71 typedef void (*i2s_dma_callback_t) (struct I2s *i2s, void *_buf, size_t len);
72 typedef void (*i2s_dma_start_streaming_t) (struct I2s *i2s, void *buf, size_t len, size_t slice_len);
73 typedef void (*i2s_dma_wait_t) (struct I2s *i2s);
74 typedef void (*i2s_dma_stop_t) (struct I2s *i2s);
76 typedef struct I2sContext
79 i2s_dma_tx_buf_t tx_buf;
80 i2s_dma_tx_is_finished_t tx_isFinish;
81 i2s_dma_callback_t tx_callback;
82 i2s_dma_start_streaming_t tx_start;
83 i2s_dma_wait_t tx_wait;
84 i2s_dma_stop_t tx_stop;
88 i2s_dma_rx_buf_t rx_buf;
89 i2s_dma_rx_is_finished_t rx_isFinish;
90 i2s_dma_callback_t rx_callback;
91 i2s_dma_start_streaming_t rx_start;
92 i2s_dma_wait_t rx_wait;
93 i2s_dma_stop_t rx_stop;
103 struct I2sHardware *hw;
106 INLINE int i2s_write(I2s *i2s, uint32_t sample)
108 ASSERT(i2s->ctx.write);
109 return i2s->ctx.write(i2s, sample);
113 INLINE uint32_t i2s_read(I2s *i2s)
115 ASSERT(i2s->ctx.read);
116 return i2s->ctx.read(i2s);
120 * Check if a dma transfer is finished.
122 * Useful for kernel-less applications.
124 INLINE bool i2s_dmaTxIsFinished(I2s *i2s)
126 ASSERT(i2s->ctx.tx_isFinish);
127 return i2s->ctx.tx_isFinish(i2s);
130 INLINE bool i2s_dmaRxIsFinished(I2s *i2s)
132 ASSERT(i2s->ctx.rx_isFinish);
133 return i2s->ctx.rx_isFinish(i2s);
136 INLINE void i2s_dmaTxBuffer(I2s *i2s, void *buf, size_t len)
138 ASSERT(i2s->ctx.tx_buf);
139 i2s->ctx.tx_buf(i2s, buf, len);
142 INLINE void i2s_dmaRxBuffer(I2s *i2s, void *buf, size_t len)
144 ASSERT(i2s->ctx.rx_buf);
145 i2s->ctx.rx_buf(i2s, buf, len);
149 INLINE void i2s_dmaTxWait(I2s *i2s)
151 ASSERT(i2s->ctx.tx_wait);
152 i2s->ctx.tx_wait(i2s);
156 INLINE void i2s_dmaStartTxStreaming(I2s *i2s, void *buf, size_t len, size_t slice_len, i2s_dma_callback_t callback)
158 ASSERT(i2s->ctx.tx_start);
159 ASSERT(len % slice_len == 0);
162 i2s->ctx.tx_callback = callback;
163 i2s->ctx.tx_slice_len = slice_len;
164 i2s->ctx.tx_start(i2s, buf, len, slice_len);
167 INLINE void i2s_dmaTxStop(I2s *i2s)
169 ASSERT(i2s->ctx.tx_stop);
170 i2s->ctx.tx_stop(i2s);
173 INLINE void i2s_dmaStartRxStreaming(I2s *i2s, void *buf, size_t len, size_t slice_len, i2s_dma_callback_t callback)
175 ASSERT(i2s->ctx.rx_start);
176 ASSERT(len % slice_len == 0);
179 i2s->ctx.rx_callback = callback;
180 i2s->ctx.rx_slice_len = slice_len;
181 i2s->ctx.rx_start(i2s, buf, len, slice_len);
184 INLINE void i2s_dmaRxStop(I2s *i2s)
186 ASSERT(i2s->ctx.rx_stop);
187 i2s->ctx.rx_stop(i2s);
190 void i2s_init(I2s *i2s, int channel);
192 /** \} */ //defgroup i2s
193 #endif /* DRV_I2S_H */