4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief AFSK1200 modem.
36 * \author Francesco Sacchi <asterix@develer.com>
42 #include "cfg/cfg_afsk.h"
43 #include "hw/hw_afsk.h"
45 #include <drv/timer.h>
47 #include <cfg/module.h>
49 #define LOG_LEVEL AFSK_LOG_LEVEL
50 #define LOG_FORMAT AFSK_LOG_FORMAT
53 #include <cpu/power.h>
55 #include <struct/fifobuf.h>
57 #include <string.h> /* memset */
62 #define PHASE_MAX (SAMPLEPERBIT * PHASE_BIT)
63 #define PHASE_THRES (PHASE_MAX / 2) // - PHASE_BIT / 2)
65 // Modulator constants
66 #define MARK_FREQ 1200
67 #define MARK_INC (uint16_t)(DIV_ROUND(SIN_LEN * (uint32_t)MARK_FREQ, CONFIG_AFSK_DAC_SAMPLERATE))
69 #define SPACE_FREQ 2200
70 #define SPACE_INC (uint16_t)(DIV_ROUND(SIN_LEN * (uint32_t)SPACE_FREQ, CONFIG_AFSK_DAC_SAMPLERATE))
72 //Ensure sample rate is a multiple of bit rate
73 STATIC_ASSERT(!(CONFIG_AFSK_DAC_SAMPLERATE % BITRATE));
75 #define DAC_SAMPLEPERBIT (CONFIG_AFSK_DAC_SAMPLERATE / BITRATE)
78 * Sine table for the first quarter of wave.
79 * The rest of the wave is computed from this first quarter.
80 * This table is used to generate the modulated data.
82 static const uint8_t PROGMEM sin_table[] =
84 128, 129, 131, 132, 134, 135, 137, 138, 140, 142, 143, 145, 146, 148, 149, 151,
85 152, 154, 155, 157, 158, 160, 162, 163, 165, 166, 167, 169, 170, 172, 173, 175,
86 176, 178, 179, 181, 182, 183, 185, 186, 188, 189, 190, 192, 193, 194, 196, 197,
87 198, 200, 201, 202, 203, 205, 206, 207, 208, 210, 211, 212, 213, 214, 215, 217,
88 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233,
89 234, 234, 235, 236, 237, 238, 238, 239, 240, 241, 241, 242, 243, 243, 244, 245,
90 245, 246, 246, 247, 248, 248, 249, 249, 250, 250, 250, 251, 251, 252, 252, 252,
91 253, 253, 253, 253, 254, 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255,
94 #define SIN_LEN 512 ///< Full wave length
96 STATIC_ASSERT(sizeof(sin_table) == SIN_LEN / 4);
100 * Given the index, this function computes the correct sine sample
101 * based only on the first quarter of wave.
103 INLINE uint8_t sin_sample(uint16_t idx)
105 ASSERT(idx < SIN_LEN);
106 uint16_t new_idx = idx % (SIN_LEN / 2);
107 new_idx = (new_idx >= (SIN_LEN / 4)) ? (SIN_LEN / 2 - new_idx - 1) : new_idx;
110 uint8_t data = pgm_read_char(&sin_table[new_idx]);
112 uint8_t data = sin_table[new_idx];
115 return (idx >= (SIN_LEN / 2)) ? (255 - data) : data;
119 #define BIT_DIFFER(bitline1, bitline2) (((bitline1) ^ (bitline2)) & 0x01)
120 #define EDGE_FOUND(bitline) BIT_DIFFER((bitline), (bitline) >> 1)
123 * High-Level Data Link Control parsing function.
124 * Parse bitstream in order to find characters.
126 * \param hdlc HDLC context.
127 * \param bit current bit to be parsed.
128 * \param fifo FIFO buffer used to push characters.
130 * \return true if all is ok, false if the fifo is full.
132 static bool hdlc_parse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
136 hdlc->demod_bits <<= 1;
137 hdlc->demod_bits |= bit ? 1 : 0;
140 if (hdlc->demod_bits == HDLC_FLAG)
142 if (!fifo_isfull(fifo))
144 fifo_push(fifo, HDLC_FLAG);
145 hdlc->rxstart = true;
150 hdlc->rxstart = false;
159 if ((hdlc->demod_bits & HDLC_RESET) == HDLC_RESET)
161 hdlc->rxstart = false;
169 if ((hdlc->demod_bits & 0x3f) == 0x3e)
172 if (hdlc->demod_bits & 0x01)
173 hdlc->currchar |= 0x80;
175 if (++hdlc->bit_idx >= 8)
177 if ((hdlc->currchar == HDLC_FLAG
178 || hdlc->currchar == HDLC_RESET
179 || hdlc->currchar == AX25_ESC))
181 if (!fifo_isfull(fifo))
182 fifo_push(fifo, AX25_ESC);
185 hdlc->rxstart = false;
190 if (!fifo_isfull(fifo))
191 fifo_push(fifo, hdlc->currchar);
194 hdlc->rxstart = false;
202 hdlc->currchar >>= 1;
210 * This function has to be called by the ADC ISR when a sample of the configured
211 * channel is available.
212 * \param af Afsk context to operate on.
213 * \param curr_sample current sample from the ADC.
215 void afsk_adc_isr(Afsk *af, int8_t curr_sample)
220 * Frequency discriminator and LP IIR filter.
221 * This filter is designed to work
222 * at the given sample rate and bit rate.
224 STATIC_ASSERT(SAMPLERATE == 9600);
225 STATIC_ASSERT(BITRATE == 1200);
228 * Frequency discrimination is achieved by simply multiplying
229 * the sample with a delayed sample of (samples per bit) / 2.
230 * Then the signal is lowpass filtered with a first order,
231 * 600 Hz filter. The filter implementation is selectable
232 * through the CONFIG_AFSK_FILTER config variable.
235 af->iir_x[0] = af->iir_x[1];
237 #if (CONFIG_AFSK_FILTER == AFSK_BUTTERWORTH)
238 af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) >> 2;
239 //af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) / 6.027339492;
240 #elif (CONFIG_AFSK_FILTER == AFSK_CHEBYSHEV)
241 af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) >> 2;
242 //af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) / 3.558147322;
244 #error Filter type not found!
247 af->iir_y[0] = af->iir_y[1];
249 #if CONFIG_AFSK_FILTER == AFSK_BUTTERWORTH
251 * This strange sum + shift is an optimization for af->iir_y[0] * 0.668.
252 * iir * 0.668 ~= (iir * 21) / 32 =
253 * = (iir * 16) / 32 + (iir * 4) / 32 + iir / 32 =
254 * = iir / 2 + iir / 8 + iir / 32 =
255 * = iir >> 1 + iir >> 3 + iir >> 5
257 af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + (af->iir_y[0] >> 1) + (af->iir_y[0] >> 3) + (af->iir_y[0] >> 5);
258 //af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + af->iir_y[0] * 0.6681786379;
259 #elif CONFIG_AFSK_FILTER == AFSK_CHEBYSHEV
261 * This should be (af->iir_y[0] * 0.438) but
262 * (af->iir_y[0] >> 1) is a faster approximation :-)
264 af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + (af->iir_y[0] >> 1);
265 //af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + af->iir_y[0] * 0.4379097269;
268 /* Save this sampled bit in a delay line */
269 af->sampled_bits <<= 1;
270 af->sampled_bits |= (af->iir_y[1] > 0) ? 1 : 0;
272 /* Store current ADC sample in the af->delay_fifo */
273 fifo_push(&af->delay_fifo, curr_sample);
275 /* If there is an edge, adjust phase sampling */
276 if (EDGE_FOUND(af->sampled_bits))
278 if (af->curr_phase < PHASE_THRES)
279 af->curr_phase += PHASE_INC;
281 af->curr_phase -= PHASE_INC;
283 af->curr_phase += PHASE_BIT;
286 if (af->curr_phase >= PHASE_MAX)
288 af->curr_phase %= PHASE_MAX;
290 /* Shift 1 position in the shift register of the found bits */
291 af->found_bits <<= 1;
294 * Determine bit value by reading the last 3 sampled bits.
295 * If the number of ones is two or greater, the bit value is a 1,
297 * This algorithm presumes that there are 8 samples per bit.
299 STATIC_ASSERT(SAMPLEPERBIT == 8);
300 uint8_t bits = af->sampled_bits & 0x07;
301 if (bits == 0x07 // 111, 3 bits set to 1
302 || bits == 0x06 // 110, 2 bits
303 || bits == 0x05 // 101, 2 bits
304 || bits == 0x03 // 011, 2 bits
309 * NRZI coding: if 2 consecutive bits have the same value
310 * a 1 is received, otherwise it's a 0.
312 if (!hdlc_parse(&af->hdlc, !EDGE_FOUND(af->found_bits), &af->rx_fifo))
313 af->status |= AFSK_RXFIFO_OVERRUN;
320 static void afsk_txStart(Afsk *af)
324 af->phase_inc = MARK_INC;
328 af->preamble_len = DIV_ROUND(CONFIG_AFSK_PREAMBLE_LEN * BITRATE, 8000);
329 AFSK_DAC_IRQ_START(af->dac_ch);
331 ATOMIC(af->trailer_len = DIV_ROUND(CONFIG_AFSK_TRAILER_LEN * BITRATE, 8000));
334 #define BIT_STUFF_LEN 5
336 #define SWITCH_TONE(inc) (((inc) == MARK_INC) ? SPACE_INC : MARK_INC)
340 * This function has to be called by the DAC ISR when a sample of the configured
341 * channel has been converted out.
343 * \param af Afsk context to operate on.
345 * \return The next DAC output sample.
347 uint8_t afsk_dac_isr(Afsk *af)
351 /* Check if we are at a start of a sample cycle */
352 if (af->sample_count == 0)
356 /* We have just finished transimitting a char, get a new one. */
357 if (fifo_isempty(&af->tx_fifo) && af->trailer_len == 0)
359 AFSK_DAC_IRQ_STOP(af->dac_ch);
367 * If we have just finished sending an unstuffed byte,
368 * reset bitstuff counter.
373 af->bit_stuff = true;
376 * Handle preamble and trailer
378 if (af->preamble_len == 0)
380 if (fifo_isempty(&af->tx_fifo))
383 af->curr_out = HDLC_FLAG;
386 af->curr_out = fifo_pop(&af->tx_fifo);
391 af->curr_out = HDLC_FLAG;
394 /* Handle char escape */
395 if (af->curr_out == AX25_ESC)
397 if (fifo_isempty(&af->tx_fifo))
399 AFSK_DAC_IRQ_STOP(af->dac_ch);
405 af->curr_out = fifo_pop(&af->tx_fifo);
407 else if (af->curr_out == HDLC_FLAG || af->curr_out == HDLC_RESET)
408 /* If these chars are not escaped disable bit stuffing */
409 af->bit_stuff = false;
411 /* Start with LSB mask */
415 /* check for bit stuffing */
416 if (af->bit_stuff && af->stuff_cnt >= BIT_STUFF_LEN)
418 /* If there are more than 5 ones in a row insert a 0 */
421 af->phase_inc = SWITCH_TONE(af->phase_inc);
426 * NRZI: if we want to transmit a 1 the modulated frequency will stay
427 * unchanged; with a 0, there will be a change in the tone.
429 if (af->curr_out & af->tx_bit)
433 * - Stay on the previous tone
434 * - Increase bit stuff counter
442 * - Reset bit stuff counter
446 af->phase_inc = SWITCH_TONE(af->phase_inc);
449 /* Go to the next bit */
452 af->sample_count = DAC_SAMPLEPERBIT;
455 /* Get new sample and put it out on the DAC */
456 af->phase_acc += af->phase_inc;
457 af->phase_acc %= SIN_LEN;
461 return sin_sample(af->phase_acc);
465 static size_t afsk_read(KFile *fd, void *_buf, size_t size)
467 Afsk *af = AFSK_CAST(fd);
468 uint8_t *buf = (uint8_t *)_buf;
470 #if CONFIG_AFSK_RXTIMEOUT == 0
471 while (size-- && !fifo_isempty_locked(&af->rx_fifo))
476 #if CONFIG_AFSK_RXTIMEOUT != -1
477 ticks_t start = timer_clock();
480 while (fifo_isempty_locked(&af->rx_fifo));
483 #if CONFIG_AFSK_RXTIMEOUT != -1
484 if (timer_clock() - start > ms_to_ticks(CONFIG_AFSK_RXTIMEOUT))
485 return buf - (uint8_t *)_buf;
489 *buf++ = fifo_pop_locked(&af->rx_fifo);
492 return buf - (uint8_t *)_buf;
495 static size_t afsk_write(KFile *fd, const void *_buf, size_t size)
497 Afsk *af = AFSK_CAST(fd);
498 const uint8_t *buf = (const uint8_t *)_buf;
502 while (fifo_isfull_locked(&af->tx_fifo))
505 fifo_push_locked(&af->tx_fifo, *buf++);
509 return buf - (const uint8_t *)_buf;
512 static int afsk_flush(KFile *fd)
514 Afsk *af = AFSK_CAST(fd);
520 static int afsk_error(KFile *fd)
522 Afsk *af = AFSK_CAST(fd);
525 ATOMIC(err = af->status);
529 static void afsk_clearerr(KFile *fd)
531 Afsk *af = AFSK_CAST(fd);
532 ATOMIC(af->status = 0);
537 * Initialize an AFSK1200 modem.
538 * \param af Afsk context to operate on.
539 * \param adc_ch ADC channel used by the demodulator.
540 * \param dac_ch DAC channel used by the modulator.
542 void afsk_init(Afsk *af, int adc_ch, int dac_ch)
544 #if CONFIG_AFSK_RXTIMEOUT != -1
547 memset(af, 0, sizeof(*af));
551 fifo_init(&af->delay_fifo, (uint8_t *)af->delay_buf, sizeof(af->delay_buf));
552 fifo_init(&af->rx_fifo, af->rx_buf, sizeof(af->rx_buf));
554 /* Fill sample FIFO with 0 */
555 for (int i = 0; i < SAMPLEPERBIT / 2; i++)
556 fifo_push(&af->delay_fifo, 0);
558 fifo_init(&af->tx_fifo, af->tx_buf, sizeof(af->tx_buf));
560 AFSK_ADC_INIT(adc_ch, af);
561 AFSK_DAC_INIT(dac_ch, af);
563 LOG_INFO("MARK_INC %d, SPACE_INC %d\n", MARK_INC, SPACE_INC);
565 DB(af->fd._type = KFT_AFSK);
566 af->fd.write = afsk_write;
567 af->fd.read = afsk_read;
568 af->fd.flush = afsk_flush;
569 af->fd.error = afsk_error;
570 af->fd.clearerr = afsk_clearerr;
571 af->phase_inc = MARK_INC;