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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief Configuration file for the ADC module.
35 * \author Daniele Basile <asterix@develer.com>
42 * Module logging level.
45 * $WIZ$ value_list = "log_level"
47 #define ADC_LOG_LEVEL LOG_LVL_INFO
50 * Module logging format.
53 * $WIZ$ value_list = "log_format"
55 #define ADC_LOG_FORMAT LOG_FMT_VERBOSE
58 * Clock Frequency for ADC conversion.
61 * $WIZ$ supports = "at91"
63 #define CONFIG_ADC_CLOCK 4800000UL
66 * Minimum time for starting up a conversion [us].
70 * $WIZ$ supports = "at91"
72 #define CONFIG_ADC_STARTUP_TIME 20
75 * Minimum time for sample and hold [us].
79 * $WIZ$ supports = "at91"
81 #define CONFIG_ADC_SHTIME 834
84 * ADC Voltage Reference.
87 * $WIZ$ value_list = "avr_adc_refs"
88 * $WIZ$ supports = "avr"
90 #define CONFIG_ADC_AVR_REF ADC_AVR_AVCC
93 * ADC clock divisor from main crystal.
98 * $WIZ$ supports = "avr"
100 #define CONFIG_ADC_AVR_DIVISOR 2
103 * Enable ADC strobe for debugging ADC ISR.
105 * $WIZ$ type = "boolean"
107 #define CONFIG_ADC_STROBE 0
109 #endif /* CFG_ADC_H */