4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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9 * (at your option) any later version.
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2006 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief AFSK modem hardware-specific definitions.
37 * \author Francesco Sacchi <batt@develer.com>
45 #include <cfg/compiler.h>
46 #include <cfg/macros.h>
47 #include <cfg/module.h>
50 #define CONFIG_ADC_CLOCK 4800000UL
51 #define CONFIG_ADC_STARTUP_TIME 20
52 #define CONFIG_ADC_SHTIME 834
54 #define ADC_COMPUTED_PRESCALER ((CPU_FREQ/(2 * CONFIG_ADC_CLOCK)) - 1)
55 #define ADC_COMPUTED_STARTUPTIME (((CONFIG_ADC_STARTUP_TIME * CONFIG_ADC_CLOCK)/ 8000000UL) - 1)
56 #define ADC_COMPUTED_SHTIME (((CONFIG_ADC_SHTIME * CONFIG_ADC_CLOCK)/1000000000UL) - 1)
58 static Afsk *afsk_ctx;
62 static void __attribute__((interrupt)) hw_afsk_adc_isr(void)
64 afsk_adc_isr(afsk_ctx, ADC_LCDR - 128);
66 /* Enable block writing */
67 PIOA_OWER = DAC_PIN_MASK;
70 PIOA_ODSR = (afsk_dac_isr(afsk_ctx) << 15) & DAC_PIN_MASK;
73 PIOA_ODSR = 0x4000000;
75 PIOA_OWDR = DAC_PIN_MASK;
80 void hw_afsk_adc_init(int ch, struct Afsk * ctx)
83 afsk_ctx->adc_ch = ch;
85 ADC_MR |= BV(ADC_LOWRES);
87 //Apply computed prescaler value
88 ADC_MR &= ~ADC_PRESCALER_MASK;
89 ADC_MR |= ((ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
91 //Apply computed start up time
92 ADC_MR &= ~ADC_STARTUP_MASK;
93 ADC_MR |= ((ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
95 //Apply computed sample and hold time
96 ADC_MR &= ~ADC_SHTIME_MASK;
97 ADC_MR |= ((ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
99 // Disable all interrupt
100 ADC_IDR = 0xFFFFFFFF;
102 //Register interrupt vector
103 AIC_SVR(ADC_ID) = hw_afsk_adc_isr;
104 AIC_SMR(ADC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
105 AIC_IECR = BV(ADC_ID);
107 //Enable data ready irq
108 ADC_IER = BV(ADC_DRDY);
111 PMC_PCER = BV(TC0_ID);
113 TC0_CCR = BV(TC_SWTRG) | BV(TC_CLKEN);
115 TC0_CMR = BV(TC_WAVE);
116 TC0_CMR |= (TC_WAVSEL_UP_RC_TRG | TC_ACPC_CLEAR_OUTPUT | TC_ACPA_SET_OUTPUT);
117 TC0_RC = (CPU_FREQ / 2) / 9600;
121 // Auto trigger enabled on TIOA channel 0
122 ADC_MR |= BV(ADC_TRGEN);
124 //Disable all channels
125 ADC_CHDR = ADC_CH_MASK;