4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
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11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief Some ADC utilis.
35 * \author Daniele Basile <asterix@develer.com>
42 #include <drv/clock_lm3s.h>
47 * Return the cpu core temperature in raw format
49 INLINE uint16_t hw_readRawTemp(void)
51 /* Trig the temperature sampling */
52 HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
54 /* Poll untill acquisition end */
55 while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
57 return (uint16_t)HWREG(ADC0_BASE + ADC_O_SSFIFO3);
61 * Return the cpu core temperature in degrees C*100
63 INLINE uint16_t hw_readIntTemp(void)
65 /* Trig the temperature sampling */
66 HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
68 /* Poll untill acquisition end */
69 while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
71 return (uint16_t)(14750 - ADC_RANGECONV(HWREG(ADC0_BASE + ADC_O_SSFIFO3), 0, 300) * 75);
74 INLINE void hw_initIntTemp(void)
76 /* Enable ADC0 clock */
77 SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0;
80 * We wait some time because the clock is istable
81 * and that could cause system hardfault
85 /* Disable all sequence */
86 HWREG(ADC0_BASE + ADC_O_ACTSS) = 0;
87 /* Set trigger event to programmed (for all sequence) */
88 HWREG(ADC0_BASE + ADC_O_EMUX) = 0;
89 /* Enalbe read of temperature sensor */
90 HWREG(ADC0_BASE + ADC_O_SSCTL3) |= ADC_SSCTL3_TS0;
91 /* Enable sequence S03 (single sample on select channel) */
92 HWREG(ADC0_BASE + ADC_O_ACTSS) |= ADC_ACTSS_ASEN3;