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33 * \brief HX8347 low-level hardware macros for Atmel SAM3X-EK board.
35 * The LCD controller is connected to the cpu static memory controller.
36 * LCD has 16 data lines and usual RS/WR/RD lines. The data lines
37 * are connected to the SMC data bus (D0-15), while the SCM address bus
38 * (A1 only) is used to drive the RS pin. WR/RD are connected to SMC's
39 * NWE and NRD respectively.
41 * \author Stefano Fedrigo <aleph@develer.com>
47 #include "cfg/macros.h"
49 #include <drv/timer.h>
53 * LCD I/O pins/ports and peripherals
55 #define LCD_DATABUS_PINS (0xFFFF << 2)
56 #define LCD_DATABUS_PORT PIOC_BASE
57 #define LCD_DATABUS_PERIPH PIO_PERIPH_A
59 #define LCD_NRD_PIN BV(29)
60 #define LCD_NRD_PORT PIOA_BASE
61 #define LCD_NRD_PERIPH PIO_PERIPH_B
63 #define LCD_NWE_PIN BV(18)
64 #define LCD_NWE_PORT PIOC_BASE
65 #define LCD_NWE_PERIPH PIO_PERIPH_A
67 #define LCD_NCS2_PIN BV(24)
68 #define LCD_NCS2_PORT PIOB_BASE
69 #define LCD_NCS2_PERIPH PIO_PERIPH_B
71 #define LCD_RS_PIN BV(22)
72 #define LCD_RS_PORT PIOC_BASE
73 #define LCD_RS_PERIPH PIO_PERIPH_A
76 // How many cpu clocks per nanosecond.
77 #define CLOCKS_PER_NS(ns) ((uint32_t)((ns * (CPU_FREQ/1000000)) / 1000) + 1)
80 // LCD Base Address, chip select 2
81 #define LCD_BASE 0x62000000
83 // LCD index register address
84 #define LCD_IR (*(uint16_t *)(LCD_BASE))
86 // LCD data address (A1 drives RS signal)
87 #define LCD_D (*(uint16_t *)(LCD_BASE + 2))
90 * Send a command to LCD controller.
92 INLINE void hx8347_cmd(uint8_t cmd)
98 * Send data to LCD controller.
100 INLINE void hx8347_write(uint16_t data)
106 * Read data from LCD controller.
108 INLINE uint16_t hx8347_read(void)
114 * Bus initialization: on SAM3X-EK the display is wired
115 * on the static memory controller, chip select 2.
117 INLINE void hx8347_busInit(void)
119 // Configure pins: disable PIO...
120 HWREG(LCD_DATABUS_PORT + PIO_PDR_OFF) = LCD_DATABUS_PINS;
121 HWREG(LCD_NRD_PORT + PIO_PDR_OFF) = LCD_NRD_PIN;
122 HWREG(LCD_NWE_PORT + PIO_PDR_OFF) = LCD_NWE_PIN;
123 HWREG(LCD_NCS2_PORT + PIO_PDR_OFF) = LCD_NCS2_PIN;
124 HWREG(LCD_RS_PORT + PIO_PDR_OFF) = LCD_RS_PIN;
126 // ... enable pull-up...
127 HWREG(LCD_DATABUS_PORT + PIO_PUER_OFF) = LCD_DATABUS_PINS;
128 HWREG(LCD_NRD_PORT + PIO_PUER_OFF) = LCD_NRD_PIN;
129 HWREG(LCD_NWE_PORT + PIO_PUER_OFF) = LCD_NWE_PIN;
130 HWREG(LCD_NCS2_PORT + PIO_PUER_OFF) = LCD_NCS2_PIN;
131 HWREG(LCD_RS_PORT + PIO_PUER_OFF) = LCD_RS_PIN;
133 // ... and select appropriate peripheral.
134 PIO_PERIPH_SEL(LCD_DATABUS_PORT, LCD_DATABUS_PINS, LCD_DATABUS_PERIPH);
135 PIO_PERIPH_SEL(LCD_NRD_PORT, LCD_NRD_PIN, LCD_NRD_PERIPH);
136 PIO_PERIPH_SEL(LCD_NWE_PORT, LCD_NWE_PIN, LCD_NWE_PERIPH);
137 PIO_PERIPH_SEL(LCD_NCS2_PORT, LCD_NCS2_PIN, LCD_NCS2_PERIPH);
138 PIO_PERIPH_SEL(LCD_RS_PORT, LCD_RS_PIN, LCD_RS_PERIPH);
140 // Enable peripheral clock
141 pmc_periphEnable(SMC_SDRAMC_ID);
143 // Static memory controller configuration
145 SMC_SETUP_NWE_SETUP(CLOCKS_PER_NS(10)) |
146 SMC_SETUP_NCS_WR_SETUP(CLOCKS_PER_NS(10)) |
147 SMC_SETUP_NRD_SETUP(CLOCKS_PER_NS(90)) |
148 SMC_SETUP_NCS_RD_SETUP(CLOCKS_PER_NS(90));
151 SMC_PULSE_NWE_PULSE(CLOCKS_PER_NS(35)) |
152 SMC_PULSE_NCS_WR_PULSE(CLOCKS_PER_NS(35)) |
153 SMC_PULSE_NRD_PULSE(CLOCKS_PER_NS(355)) |
154 SMC_PULSE_NCS_RD_PULSE(CLOCKS_PER_NS(355));
157 SMC_CYCLE_NWE_CYCLE(CLOCKS_PER_NS(100)) |
158 SMC_CYCLE_NRD_CYCLE(CLOCKS_PER_NS(460));
161 SMC_MODE_WRITE_MODE | SMC_MODE_READ_MODE | SMC_MODE_DBW;
164 #endif /* HW_HX8347_H */