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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief MT48LC16M16A2 SDRAM initialization for Atmel SAM3X-EK board.
35 * \author Stefano Fedrigo <aleph@develer.com>
37 * SDRAMC register settings and comments are from Atmel Softpack, see licence below:
39 * ----------------------------------------------------------------------------
40 * ATMEL Microcontroller Software Support
41 * ----------------------------------------------------------------------------
42 * Copyright (c) 2010, Atmel Corporation
44 * All rights reserved.
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions are met:
49 * - Redistributions of source code must retain the above copyright notice,
50 * this list of conditions and the disclaimer below.
52 * Atmel's name may not be used to endorse or promote products derived from
53 * this software without specific prior written permission.
55 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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57 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
58 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
61 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
62 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
63 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
64 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 * ----------------------------------------------------------------------------
68 #ifndef HW_SAM3X_SDRAM_H
69 #define HW_SAM3X_SDRAM_H
71 #include "cfg/macros.h"
72 #include <cpu/types.h>
74 #include <drv/timer.h>
79 #define SDRAM_BASE 0x70000000
80 #define SDRAM_SIZE (32*1024*1024)
81 #define SDRAM_BUSWIDTH 16
82 #define SDRAM_CLK CPU_FREQ
87 // port C, peripheral A
88 #define PIO_SDRAM_DATA (0xFFFF << 2) // Data bus, 2-17
89 #define PIO_SDRAM_SDA0_A7 (0xFF << 23) // Address bus, 23-30
90 #define PIO_SDRAM_NBS0 BV(21) // Data mask enable 0
91 // port D, peripheral A
92 #define PIO_SDRAM_SDCKE BV(13) // Clock enable
93 #define PIO_SDRAM_SDCS BV(12) // Chip select
94 #define PIO_SDRAM_RAS BV(15) // Row
95 #define PIO_SDRAM_CAS BV(16) // Column
96 #define PIO_SDRAM_BA0 BV(6) // Bank select 0
97 #define PIO_SDRAM_BA1 BV(7) // Bank select 1
98 #define PIO_SDRAM_SDWE BV(14) // Write enable
99 #define PIO_SDRAM_NBS1 BV(10) // Data mask enable 1
100 #define PIO_SDRAM_SDA8 BV(22)
101 #define PIO_SDRAM_SDA9 BV(23)
102 #define PIO_SDRAM_SDA10 BV(11)
103 #define PIO_SDRAM_SDA11 BV(25)
104 #define PIO_SDRAM_SDA12 BV(4)
105 // port D, PIO output
106 #define PIO_SDRAM_EN BV(18) // Enable
108 #define SDRAM_PORTC_PERIPH (PIO_SDRAM_DATA | PIO_SDRAM_SDA0_A7 | PIO_SDRAM_NBS0)
109 #define SDRAM_PORTD_PERIPH (PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS | PIO_SDRAM_RAS | \
110 PIO_SDRAM_CAS | PIO_SDRAM_BA0 | PIO_SDRAM_BA1 | \
111 PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 | PIO_SDRAM_SDA8 | \
112 PIO_SDRAM_SDA9 | PIO_SDRAM_SDA10 | PIO_SDRAM_SDA11 | \
114 #define SDRAM_PORTD_OUTPUT PIO_SDRAM_EN
117 INLINE void sdram_init(void)
119 HWREG(PIOC_BASE + PIO_PDR_OFF) = SDRAM_PORTC_PERIPH;
120 HWREG(PIOC_BASE + PIO_PUER_OFF) = SDRAM_PORTC_PERIPH;
121 PIO_PERIPH_SEL(PIOC_BASE, SDRAM_PORTC_PERIPH, PIO_PERIPH_A);
123 HWREG(PIOD_BASE + PIO_PDR_OFF) = SDRAM_PORTD_PERIPH;
124 HWREG(PIOD_BASE + PIO_PUER_OFF) = SDRAM_PORTD_PERIPH;
125 PIO_PERIPH_SEL(PIOD_BASE, SDRAM_PORTD_PERIPH, PIO_PERIPH_A);
127 HWREG(PIOD_BASE + PIO_PER_OFF) = SDRAM_PORTD_OUTPUT;
128 HWREG(PIOD_BASE + PIO_OER_OFF) = SDRAM_PORTD_OUTPUT;
129 HWREG(PIOD_BASE + PIO_SODR_OFF) = SDRAM_PORTD_OUTPUT;
131 pmc_periphEnable(SMC_SDRAMC_ID);
133 // SDRAM device configuration
135 SDRAMC_CR_NC_COL9 | SDRAMC_CR_NR_ROW13 | SDRAMC_CR_NB_BANK4 |
136 SDRAMC_CR_CAS_LATENCY2 | SDRAMC_CR_DBW |
137 SDRAMC_CR_TWR(2) | SDRAMC_CR_TRC_TRFC(9) | SDRAMC_CR_TRP(3) |
138 SDRAMC_CR_TRCD(3) | SDRAMC_CR_TRAS(6) | SDRAMC_CR_TXSR(10);
141 SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
144 * A minimum pause of 200 us needed before any signal toggle
145 * (6 core cycles per iteration).
150 * A NOP command is issued to the SDR-SDRAM. Program NOP command into
151 * Mode Register, the application must set Mode to 1 in the Mode Register.
152 * Perform a write access to any SDR-SDRAM address to acknowledge this command.
153 * Now the clock which drives SDR-SDRAM device is enabled.
155 SDRAMC_MR = SDRAMC_MR_MODE_NOP;
156 *(uint32_t *)SDRAM_BASE = 0;
159 * An all banks precharge command is issued to the SDR-SDRAM. Program all
160 * banks precharge command into Mode Register, the application must set Mode to
161 * 2 in the Mode Register . Perform a write access to any SDRSDRAM address to
162 * acknowledge this command.
164 SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
165 *(uint32_t *)SDRAM_BASE = 0;
168 * Eight auto-refresh (CBR) cycles are provided. Program the auto refresh
169 * command (CBR) into Mode Register, the application must set Mode to 4 in
170 * the Mode Register. Once in the idle state, two AUTO REFRESH cycles must
173 SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
174 *(uint32_t *)SDRAM_BASE = 0;
176 SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
177 *(uint32_t *)SDRAM_BASE = 0;
180 * A Mode Register set (MRS) cycle is issued to program the parameters of
181 * the SDRAM devices, in particular CAS latency and burst length.
183 SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
184 *(uint32_t *)(SDRAM_BASE + 9) = 0xc001babe;
187 * For low-power SDR-SDRAM initialization, an Extended Mode Register set
188 * (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS).
189 * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set
190 * to 0: BK1 is at bit 24, 1+9+13+1.
192 SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
193 *(uint32_t *)(SDRAM_BASE + (1 << 24)) = 0;
196 * The application must go into Normal Mode, setting Mode to 0 in the Mode
197 * Register and perform a write access at any location in the SDRAM to
198 * acknowledge this command.
200 SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
201 *(uint32_t *)SDRAM_BASE = 0;
204 * Write the refresh rate into the count field in the SDRAMC Refresh
205 * Timer register. Set Refresh timer 15.625 us
207 SDRAMC_TR = SDRAMC_TR_COUNT(SDRAM_CLK / 1000 * 15625 / 1000000) ;
210 #endif /* HW_SAM3X_SDRAM_H */