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33 * \brief MT48LC16M16A2 SDRAM initialization for Atmel SAM3X-EK board.
35 * \author Stefano Fedrigo <aleph@develer.com>
37 * SDRAMC register settings and comments are from Atmel Softpack, see licence below:
39 * ----------------------------------------------------------------------------
40 * ATMEL Microcontroller Software Support
41 * ----------------------------------------------------------------------------
42 * Copyright (c) 2010, Atmel Corporation
44 * All rights reserved.
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions are met:
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50 * this list of conditions and the disclaimer below.
52 * Atmel's name may not be used to endorse or promote products derived from
53 * this software without specific prior written permission.
55 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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64 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 * ----------------------------------------------------------------------------
68 #ifndef HW_SAM3X_SDRAM_H
69 #define HW_SAM3X_SDRAM_H
71 #include "cfg/macros.h"
77 #define SDRAM_BASE 0x70000000
78 #define SDRAM_SIZE (32*1024*1024)
79 #define SDRAM_BUSWIDTH 16
80 #define SDRAM_CLK CPU_FREQ
85 // port C, peripheral A
86 #define PIO_SDRAM_DATA (0xFFFF << 2) // Data bus, 2-17
87 #define PIO_SDRAM_SDA0_A7 (0xFF << 23) // Address bus, 23-30
88 #define PIO_SDRAM_NBS0 BV(21) // Data mask enable 0
89 // port D, peripheral A
90 #define PIO_SDRAM_SDCKE BV(13) // Clock enable
91 #define PIO_SDRAM_SDCS BV(12) // Chip select
92 #define PIO_SDRAM_RAS BV(15) // Row
93 #define PIO_SDRAM_CAS BV(16) // Column
94 #define PIO_SDRAM_BA0 BV(6) // Bank select 0
95 #define PIO_SDRAM_BA1 BV(7) // Bank select 1
96 #define PIO_SDRAM_SDWE BV(14) // Write enable
97 #define PIO_SDRAM_NBS1 BV(10) // Data mask enable 1
98 #define PIO_SDRAM_SDA8 BV(22)
99 #define PIO_SDRAM_SDA9 BV(23)
100 #define PIO_SDRAM_SDA10 BV(11)
101 #define PIO_SDRAM_SDA11 BV(25)
102 #define PIO_SDRAM_SDA12 BV(4)
103 // port D, PIO output
104 #define PIO_SDRAM_EN BV(18) // Enable
106 #define SDRAM_PORTC_PERIPH (PIO_SDRAM_DATA | PIO_SDRAM_SDA0_A7 | PIO_SDRAM_NBS0)
107 #define SDRAM_PORTD_PERIPH (PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS | PIO_SDRAM_RAS | \
108 PIO_SDRAM_CAS | PIO_SDRAM_BA0 | PIO_SDRAM_BA1 | \
109 PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 | PIO_SDRAM_SDA8 | \
110 PIO_SDRAM_SDA9 | PIO_SDRAM_SDA10 | PIO_SDRAM_SDA11 | \
112 #define SDRAM_PORTD_OUTPUT PIO_SDRAM_EN
115 INLINE void sdram_init(void)
117 HWREG(PIOC_BASE + PIO_PDR_OFF) = SDRAM_PORTC_PERIPH;
118 HWREG(PIOC_BASE + PIO_PUER_OFF) = SDRAM_PORTC_PERIPH;
119 PIO_PERIPH_SEL(PIOC_BASE, SDRAM_PORTC_PERIPH, PIO_PERIPH_A);
121 HWREG(PIOD_BASE + PIO_PDR_OFF) = SDRAM_PORTD_PERIPH;
122 HWREG(PIOD_BASE + PIO_PUER_OFF) = SDRAM_PORTD_PERIPH;
123 PIO_PERIPH_SEL(PIOD_BASE, SDRAM_PORTD_PERIPH, PIO_PERIPH_A);
125 HWREG(PIOD_BASE + PIO_PER_OFF) = SDRAM_PORTD_OUTPUT;
126 HWREG(PIOD_BASE + PIO_OER_OFF) = SDRAM_PORTD_OUTPUT;
127 HWREG(PIOD_BASE + PIO_SODR_OFF) = SDRAM_PORTD_OUTPUT;
129 pmc_periphEnable(SMC_SDRAMC_ID);
131 // SDRAM device configuration
133 SDRAMC_CR_NC_COL9 | SDRAMC_CR_NR_ROW13 | SDRAMC_CR_NB_BANK4 |
134 SDRAMC_CR_CAS_LATENCY2 | SDRAMC_CR_DBW |
135 SDRAMC_CR_TWR(2) | SDRAMC_CR_TRC_TRFC(9) | SDRAMC_CR_TRP(3) |
136 SDRAMC_CR_TRCD(3) | SDRAMC_CR_TRAS(6) | SDRAMC_CR_TXSR(10);
139 SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
142 * A minimum pause of 200 us needed before any signal toggle
143 * (6 core cycles per iteration).
148 * A NOP command is issued to the SDR-SDRAM. Program NOP command into
149 * Mode Register, the application must set Mode to 1 in the Mode Register.
150 * Perform a write access to any SDR-SDRAM address to acknowledge this command.
151 * Now the clock which drives SDR-SDRAM device is enabled.
153 SDRAMC_MR = SDRAMC_MR_MODE_NOP;
154 *(uint32_t *)SDRAM_BASE = 0;
157 * An all banks precharge command is issued to the SDR-SDRAM. Program all
158 * banks precharge command into Mode Register, the application must set Mode to
159 * 2 in the Mode Register . Perform a write access to any SDRSDRAM address to
160 * acknowledge this command.
162 SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
163 *(uint32_t *)SDRAM_BASE = 0;
166 * Eight auto-refresh (CBR) cycles are provided. Program the auto refresh
167 * command (CBR) into Mode Register, the application must set Mode to 4 in
168 * the Mode Register. Once in the idle state, two AUTO REFRESH cycles must
171 SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
172 *(uint32_t *)SDRAM_BASE = 0;
174 SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
175 *(uint32_t *)SDRAM_BASE = 0;
178 * A Mode Register set (MRS) cycle is issued to program the parameters of
179 * the SDRAM devices, in particular CAS latency and burst length.
181 SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
182 *(uint32_t *)(SDRAM_BASE + 9) = 0xc001babe;
185 * For low-power SDR-SDRAM initialization, an Extended Mode Register set
186 * (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS).
187 * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set
188 * to 0: BK1 is at bit 24, 1+9+13+1.
190 SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
191 *(uint32_t *)(SDRAM_BASE + (1 << 24)) = 0;
194 * The application must go into Normal Mode, setting Mode to 0 in the Mode
195 * Register and perform a write access at any location in the SDRAM to
196 * acknowledge this command.
198 SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
199 *(uint32_t *)SDRAM_BASE = 0;
202 * Write the refresh rate into the count field in the SDRAMC Refresh
203 * Timer register. Set Refresh timer 15.625 us
205 SDRAMC_TR = SDRAMC_TR_COUNT(SDRAM_CLK / 1000 * 15625 / 1000000) ;
208 #endif /* HW_SAM3X_SDRAM_H */