4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief Configuration file for serial module.
37 * \author Daniele Basile <asterix@develer.com>
44 /// Kdebug console on debug unit
45 #define CONFIG_TRIFACE_PORT 1
47 /// Baud-rate for the kdebug console
48 #define CONFIG_TRIFACE_BAUDRATE 115200
49 /// Triface serial tag port
50 #define TAG_SER_PORT 0
51 ///Baud-rate for triface serial tag port
52 #define TAG_SER_BAUDRATE 9600
54 /// [bytes] Size of the outbound FIFO buffer for port 0.
55 #define CONFIG_UART0_TXBUFSIZE 32
57 /// [bytes] Size of the inbound FIFO buffer for port 0.
58 #define CONFIG_UART0_RXBUFSIZE 64
60 /// [bytes] Size of the outbound FIFO buffer for port 1.
61 #define CONFIG_UART1_TXBUFSIZE 32
63 /// [bytes] Size of the inbound FIFO buffer for port 1.
64 #define CONFIG_UART1_RXBUFSIZE 64
67 /// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
68 #define CONFIG_SPI_TXBUFSIZE 32
70 /// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
71 #define CONFIG_SPI_RXBUFSIZE 32
73 /// [bytes] Size of the outbound FIFO buffer for SPI port 0.
74 #define CONFIG_SPI0_TXBUFSIZE 32
76 /// [bytes] Size of the inbound FIFO buffer for SPI port 0.
77 #define CONFIG_SPI0_RXBUFSIZE 32
79 /// [bytes] Size of the outbound FIFO buffer for SPI port 1.
80 #define CONFIG_SPI1_TXBUFSIZE 32
82 /// [bytes] Size of the inbound FIFO buffer for SPI port 1.
83 #define CONFIG_SPI1_RXBUFSIZE 32
85 /// SPI data order (AVR only).
86 #define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST
88 /// SPI clock division factor (AVR only).
89 #define CONFIG_SPI_CLOCK_DIV 16
91 /// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
92 #define CONFIG_SPI_CLOCK_POL 0
94 /// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
95 #define CONFIG_SPI_CLOCK_PHASE 0
97 /// Default transmit timeout (ms). Set to -1 to disable timeout support.
98 #define CONFIG_SER_TXTIMEOUT 100
100 /// Default receive timeout (ms). Set to -1 to disable timeout support.
101 #define CONFIG_SER_RXTIMEOUT 100
103 /// Use RTS/CTS handshake
104 #define CONFIG_SER_HWHANDSHAKE 0
106 /// Default baud rate (set to 0 to disable).
107 #define CONFIG_SER_DEFBAUDRATE 0
109 /// Enable second serial port in emulator.
110 #define CONFIG_EMUL_UART1 0
113 * Transmit always something on serial port 0 TX
114 * to avoid interference when sending burst of data,
115 * using AVR multiprocessor serial mode
117 #define CONFIG_SER_TXFILL 0
119 /// For serial debug.
120 #define CONFIG_SER_STROBE 0
122 #endif /* CFG_SER_H */