4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.7 2005/11/27 03:04:38 bernie
21 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
23 *#* Revision 1.6 2005/07/19 07:26:49 bernie
24 *#* Add missing #endif.
26 *#* Revision 1.5 2005/06/27 21:24:17 bernie
27 *#* CPU_CSOURCE(): New macro.
29 *#* Revision 1.4 2005/06/14 06:15:10 bernie
30 *#* Add X86_64 support.
32 *#* Revision 1.3 2005/04/12 04:06:17 bernie
33 *#* Catch missing CPU earlier.
35 *#* Revision 1.2 2005/04/11 19:10:27 bernie
36 *#* Include top-level headers from cfg/ subdir.
38 *#* Revision 1.1 2005/04/11 19:04:13 bernie
39 *#* Move top-level headers to cfg/ subdir.
41 *#* Revision 1.30 2005/03/15 00:20:09 bernie
42 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
44 *#* Revision 1.29 2005/02/16 20:33:24 bernie
45 *#* Preliminary PPC support.
47 *#* Revision 1.28 2004/12/31 17:39:41 bernie
48 *#* Fix documentation.
50 *#* Revision 1.27 2004/12/31 17:02:47 bernie
51 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
53 *#* Revision 1.26 2004/12/13 12:08:12 bernie
54 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
56 *#* Revision 1.25 2004/12/08 08:31:02 bernie
57 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
62 #include <cfg/compiler.h> /* for uintXX_t */
66 * \name Macros for determining CPU endianness.
69 #define CPU_BIG_ENDIAN 0x1234
70 #define CPU_LITTLE_ENDIAN 0x3412
73 /*! Macro to include cpu-specific versions of the headers. */
74 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
76 /*! Macro to include cpu-specific versions of implementation files. */
77 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
82 #define NOP nop_instruction()
83 #define IRQ_DISABLE disable_interrupt()
84 #define IRQ_ENABLE enable_interrupt()
86 typedef uint16_t cpuflags_t; // FIXME
87 typedef unsigned int cpustack_t;
89 #define CPU_REG_BITS 16
90 #define CPU_REGS_CNT 16
91 #define CPU_STACK_GROWS_UPWARD 0
92 #define CPU_SP_ON_EMPTY_SLOT 0
93 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
98 #define NOP asm volatile ("nop")
100 /* Get IRQ_* definitions from the hosting environment. */
103 #define IRQ_DISABLE FIXME
104 #define IRQ_ENABLE FIXME
105 #define IRQ_SAVE_DISABLE(x) FIXME
106 #define IRQ_RESTORE(x) FIXME
107 typedef uint32_t cpuflags_t; // FIXME
108 #endif /* OS_EMBEDDED */
111 #define CPU_REGS_CNT 7
112 #define CPU_STACK_GROWS_UPWARD 0
113 #define CPU_SP_ON_EMPTY_SLOT 0
114 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
115 #define CPU_HARVARD 0
118 typedef uint64_t cpustack_t;
119 #define CPU_REG_BITS 64
122 /* WIN64 is an IL32-P64 weirdo. */
123 #define SIZEOF_LONG 4
126 typedef uint32_t cpustack_t;
127 #define CPU_REG_BITS 32
131 #define NOP asm volatile ("nop" ::)
133 #define IRQ_DISABLE FIXME
134 #define IRQ_ENABLE FIXME
135 #define IRQ_SAVE_DISABLE(x) FIXME
136 #define IRQ_RESTORE(x) FIXME
137 #define IRQ_GETSTATE() FIXME
139 typedef uint32_t cpuflags_t; // FIXME
140 typedef uint32_t cpustack_t; // FIXME
142 /* Register counts include SREG too */
143 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
144 #define CPU_REGS_CNT FIXME
145 #define CPU_SAVED_REGS_CNT FIXME
146 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
147 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
148 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
149 #define CPU_HARVARD 0
154 #define BREAKPOINT asm(debug)
155 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
156 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
158 #define IRQ_SAVE_DISABLE(x) \
159 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
160 #define IRQ_RESTORE(x) \
161 do { (void)x; asm(move x,SR); } while (0)
163 static inline bool irq_running(void)
165 extern void *user_sp;
168 #define IRQ_RUNNING() irq_running()
170 static inline bool irq_getstate(void)
174 return !(x & 0x0200);
176 #define IRQ_GETSTATE() irq_getstate()
178 typedef uint16_t cpuflags_t;
179 typedef unsigned int cpustack_t;
181 #define CPU_REG_BITS 16
182 #define CPU_REGS_CNT FIXME
183 #define CPU_SAVED_REGS_CNT 8
184 #define CPU_STACK_GROWS_UPWARD 1
185 #define CPU_SP_ON_EMPTY_SLOT 0
186 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
187 #define CPU_HARVARD 1
189 /* Memory is word-addessed in the DSP56K */
190 #define CPU_BITS_PER_CHAR 16
191 #define SIZEOF_SHORT 1
193 #define SIZEOF_LONG 2
198 #define NOP asm volatile ("nop" ::)
199 #define IRQ_DISABLE asm volatile ("cli" ::)
200 #define IRQ_ENABLE asm volatile ("sei" ::)
202 #define IRQ_SAVE_DISABLE(x) \
204 __asm__ __volatile__( \
205 "in %0,__SREG__\n\t" \
207 : "=r" (x) : /* no inputs */ : "cc" \
211 #define IRQ_RESTORE(x) \
213 __asm__ __volatile__( \
214 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
218 #define IRQ_GETSTATE() \
221 __asm__ __volatile__( \
222 "in %0,__SREG__\n\t" \
223 : "=r" (sreg) /* no inputs & no clobbers */ \
225 (bool)(sreg & 0x80); \
228 typedef uint8_t cpuflags_t;
229 typedef uint8_t cpustack_t;
231 /* Register counts include SREG too */
232 #define CPU_REG_BITS 8
233 #define CPU_REGS_CNT 33
234 #define CPU_SAVED_REGS_CNT 19
235 #define CPU_STACK_GROWS_UPWARD 0
236 #define CPU_SP_ON_EMPTY_SLOT 1
237 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
238 #define CPU_HARVARD 1
241 * Initialization value for registers in stack frame.
242 * The register index is not directly corrispondent to CPU
243 * register numbers. Index 0 is the SREG register: the initial
244 * value is all 0 but the interrupt bit (bit 7).
246 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
249 #error No CPU_... defined.
253 * Execute \a CODE atomically with respect to interrupts.
255 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
257 #define ATOMIC(CODE) \
259 cpuflags_t __flags; \
260 IRQ_SAVE_DISABLE(__flags); \
262 IRQ_RESTORE(__flags); \
266 //! Default for macro not defined in the right arch section
267 #ifndef CPU_REG_INIT_VALUE
268 #define CPU_REG_INIT_VALUE(reg) 0
272 #ifndef CPU_STACK_GROWS_UPWARD
273 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
276 #ifndef CPU_SP_ON_EMPTY_SLOT
277 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
281 * Support stack handling peculiarities of a few CPUs.
283 * Most processors let their stack grow downward and
284 * keep SP pointing at the last pushed value.
286 #if !CPU_STACK_GROWS_UPWARD
287 #if !CPU_SP_ON_EMPTY_SLOT
288 /* Most microprocessors (x86, m68k...) */
289 #define CPU_PUSH_WORD(sp, data) \
290 do { *--(sp) = (data); } while (0)
291 #define CPU_POP_WORD(sp) \
295 #define CPU_PUSH_WORD(sp, data) \
296 do { *(sp)-- = (data); } while (0)
297 #define CPU_POP_WORD(sp) \
301 #else /* CPU_STACK_GROWS_UPWARD */
303 #if !CPU_SP_ON_EMPTY_SLOT
304 /* DSP56K and other weirdos */
305 #define CPU_PUSH_WORD(sp, data) \
306 do { *++(sp) = (cpustack_t)(data); } while (0)
307 #define CPU_POP_WORD(sp) \
310 #error I bet you cannot find a CPU like this
317 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
318 * RTS discards SR while returning (it does not restore it). So we push
319 * 0 to fake the same context.
321 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
323 CPU_PUSH_WORD((sp), (func)); \
324 CPU_PUSH_WORD((sp), 0x100); \
329 * In AVR, the addresses are pushed into the stack as little-endian, while
330 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
331 * no natural endianess).
333 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
335 uint16_t funcaddr = (uint16_t)(func); \
336 CPU_PUSH_WORD((sp), funcaddr); \
337 CPU_PUSH_WORD((sp), funcaddr>>8); \
341 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
342 CPU_PUSH_WORD((sp), (func))
347 * \name Default type sizes.
349 * These defaults are reasonable for most 16/32bit machines.
350 * Some of these macros may be overridden by CPU-specific code above.
352 * ANSI C requires that the following equations be true:
354 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
355 * sizeof(float) <= sizeof(double)
356 * CPU_BITS_PER_CHAR >= 8
357 * CPU_BITS_PER_SHORT >= 8
358 * CPU_BITS_PER_INT >= 16
359 * CPU_BITS_PER_LONG >= 32
364 #define SIZEOF_CHAR 1
368 #define SIZEOF_SHORT 2
372 #if CPU_REG_BITS < 32
377 #endif /* !SIZEOF_INT */
380 #if CPU_REG_BITS > 32
381 #define SIZEOF_LONG 8
383 #define SIZEOF_LONG 4
388 #if CPU_REG_BITS < 32
390 #elif CPU_REG_BITS == 32
392 #else /* CPU_REG_BITS > 32 */
397 #ifndef CPU_BITS_PER_CHAR
398 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
401 #ifndef CPU_BITS_PER_SHORT
402 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
405 #ifndef CPU_BITS_PER_INT
406 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
409 #ifndef CPU_BITS_PER_LONG
410 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
413 #ifndef CPU_BITS_PER_PTR
414 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
418 #define BREAKPOINT /* nop */
423 /* Sanity checks for the above definitions */
424 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
425 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
426 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
427 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
428 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
429 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
430 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
431 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
432 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
433 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
434 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
435 #ifdef __HAS_INT64_T__
436 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
437 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
443 * \brief Invoked by the scheduler to stop the CPU when idle.
445 * This hook can be redefined to put the CPU in low-power mode, or to
446 * profile system load with an external strobe, or to save CPU cycles
447 * in hosted environments such as emulators.
450 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
451 /* This emulator hook should yield the CPU to the host. */
453 void SchedulerIdle(void);
455 #define CPU_IDLE SchedulerIdle()
456 #else /* !ARCH_EMUL */
457 #define CPU_IDLE do { /* nothing */ } while (0)
458 #endif /* !ARCH_EMUL */
459 #endif /* !CPU_IDLE */
462 #define SCHEDULER_IDLE CPU_IDLE
464 #endif /* DEVLIB_CPU_H */