4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.15 2006/07/19 12:56:25 bernie
21 *#* Convert to new Doxygen style.
23 *#* Revision 1.14 2006/07/19 12:54:12 bernie
24 *#* Documentation fixes.
26 *#* Revision 1.13 2006/03/27 04:49:23 bernie
27 *#* CPU_IDLE(): Fix for new emulator.
29 *#* Revision 1.12 2006/03/21 10:52:39 bernie
30 *#* Update ARM support.
32 *#* Revision 1.11 2006/03/20 17:49:00 bernie
35 *#* Revision 1.10 2006/02/24 01:17:30 bernie
36 *#* CPU_SAVED_REGS_CNT: Declare for x86/x86_64.
38 *#* Revision 1.9 2006/02/23 09:08:43 bernie
39 *#* Add note for a frequently reported non-bug.
41 *#* Revision 1.8 2006/02/10 12:37:45 bernie
42 *#* Add support for ARM on IAR.
44 *#* Revision 1.7 2005/11/27 03:04:38 bernie
45 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
47 *#* Revision 1.6 2005/07/19 07:26:49 bernie
48 *#* Add missing #endif.
50 *#* Revision 1.5 2005/06/27 21:24:17 bernie
51 *#* CPU_CSOURCE(): New macro.
53 *#* Revision 1.4 2005/06/14 06:15:10 bernie
54 *#* Add X86_64 support.
56 *#* Revision 1.3 2005/04/12 04:06:17 bernie
57 *#* Catch missing CPU earlier.
59 *#* Revision 1.2 2005/04/11 19:10:27 bernie
60 *#* Include top-level headers from cfg/ subdir.
62 *#* Revision 1.1 2005/04/11 19:04:13 bernie
63 *#* Move top-level headers to cfg/ subdir.
65 *#* Revision 1.30 2005/03/15 00:20:09 bernie
66 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
68 *#* Revision 1.29 2005/02/16 20:33:24 bernie
69 *#* Preliminary PPC support.
71 *#* Revision 1.28 2004/12/31 17:39:41 bernie
72 *#* Fix documentation.
74 *#* Revision 1.27 2004/12/31 17:02:47 bernie
75 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
77 *#* Revision 1.26 2004/12/13 12:08:12 bernie
78 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
80 *#* Revision 1.25 2004/12/08 08:31:02 bernie
81 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
86 #include <cfg/compiler.h> /* for uintXX_t */
87 #include <cfg/arch_config.h> /* ARCH_EMUL */
91 * \name Macros for determining CPU endianness.
94 #define CPU_BIG_ENDIAN 0x1234
95 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
98 /** Macro to include cpu-specific versions of the headers. */
99 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
101 /** Macro to include cpu-specific versions of implementation files. */
102 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
107 #define NOP nop_instruction()
108 #define IRQ_DISABLE disable_interrupt()
109 #define IRQ_ENABLE enable_interrupt()
111 typedef uint16_t cpuflags_t; // FIXME
112 typedef unsigned int cpustack_t;
114 #define CPU_REG_BITS 16
115 #define CPU_REGS_CNT 16
116 #define CPU_STACK_GROWS_UPWARD 0
117 #define CPU_SP_ON_EMPTY_SLOT 0
118 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
119 #define CPU_HARVARD 0
123 #define NOP asm volatile ("nop")
125 /* Get IRQ_* definitions from the hosting environment. */
128 #define IRQ_DISABLE FIXME
129 #define IRQ_ENABLE FIXME
130 #define IRQ_SAVE_DISABLE(x) FIXME
131 #define IRQ_RESTORE(x) FIXME
132 typedef uint32_t cpuflags_t; // FIXME
133 #endif /* OS_EMBEDDED */
136 #define CPU_REGS_CNT 7
137 #define CPU_SAVED_REGS_CNT 7
138 #define CPU_STACK_GROWS_UPWARD 0
139 #define CPU_SP_ON_EMPTY_SLOT 0
140 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
141 #define CPU_HARVARD 0
144 typedef uint64_t cpustack_t;
145 #define CPU_REG_BITS 64
148 /* WIN64 is an IL32-P64 weirdo. */
149 #define SIZEOF_LONG 4
152 typedef uint32_t cpustack_t;
153 #define CPU_REG_BITS 32
158 typedef uint32_t cpuflags_t;
159 typedef uint32_t cpustack_t;
161 /* Register counts include SREG too */
162 #define CPU_REG_BITS 32
163 #define CPU_REGS_CNT 16
164 #define CPU_SAVED_REGS_CNT FIXME
165 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
166 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
167 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
168 #define CPU_HARVARD 0
170 #ifdef __IAR_SYSTEMS_ICC__
174 #if __CPU_MODE__ == 1 /* Thumb */
176 extern cpuflags_t get_CPSR(void);
177 extern void set_CPSR(cpuflags_t flags);
179 #define get_CPSR __get_CPSR
180 #define set_CPSR __set_CPSR
183 #define NOP __no_operation()
184 #define IRQ_DISABLE __disable_interrupt()
185 #define IRQ_ENABLE __enable_interrupt()
187 #define IRQ_SAVE_DISABLE(x) \
190 __disable_interrupt(); \
193 #define IRQ_RESTORE(x) \
198 #define IRQ_GETSTATE() \
199 ((bool)(get_CPSR() & 0xb0))
201 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
203 #else /* !__IAR_SYSTEMS_ICC__ */
205 #warning "IRQ_ macros need testing!"
207 #define NOP asm volatile ("mov r0,r0" ::)
209 #define IRQ_DISABLE \
213 "orr r0, r0, #0xb0\n\t" \
223 "bic r0, r0, #0xb0\n\t" \
229 #define IRQ_SAVE_DISABLE(x) \
234 "orr r0, r0, #0xb0\n\t" \
242 #define IRQ_RESTORE(x) \
253 #define IRQ_GETSTATE() \
263 (bool)(sreg & 0xb0); \
266 #endif /* __IAR_SYSTEMS_ICC_ */
269 #define NOP asm volatile ("nop" ::)
271 #define IRQ_DISABLE FIXME
272 #define IRQ_ENABLE FIXME
273 #define IRQ_SAVE_DISABLE(x) FIXME
274 #define IRQ_RESTORE(x) FIXME
275 #define IRQ_GETSTATE() FIXME
277 typedef uint32_t cpuflags_t; // FIXME
278 typedef uint32_t cpustack_t; // FIXME
280 /* Register counts include SREG too */
281 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
282 #define CPU_REGS_CNT FIXME
283 #define CPU_SAVED_REGS_CNT FIXME
284 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
285 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
286 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
287 #define CPU_HARVARD 0
292 #define BREAKPOINT asm(debug)
293 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
294 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
296 #define IRQ_SAVE_DISABLE(x) \
297 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
298 #define IRQ_RESTORE(x) \
299 do { (void)x; asm(move x,SR); } while (0)
301 static inline bool irq_running(void)
303 extern void *user_sp;
306 #define IRQ_RUNNING() irq_running()
308 static inline bool irq_getstate(void)
312 return !(x & 0x0200);
314 #define IRQ_GETSTATE() irq_getstate()
316 typedef uint16_t cpuflags_t;
317 typedef unsigned int cpustack_t;
319 #define CPU_REG_BITS 16
320 #define CPU_REGS_CNT FIXME
321 #define CPU_SAVED_REGS_CNT 8
322 #define CPU_STACK_GROWS_UPWARD 1
323 #define CPU_SP_ON_EMPTY_SLOT 0
324 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
325 #define CPU_HARVARD 1
327 /* Memory is word-addessed in the DSP56K */
328 #define CPU_BITS_PER_CHAR 16
329 #define SIZEOF_SHORT 1
331 #define SIZEOF_LONG 2
336 #define NOP asm volatile ("nop" ::)
337 #define IRQ_DISABLE asm volatile ("cli" ::)
338 #define IRQ_ENABLE asm volatile ("sei" ::)
340 #define IRQ_SAVE_DISABLE(x) \
342 __asm__ __volatile__( \
343 "in %0,__SREG__\n\t" \
345 : "=r" (x) : /* no inputs */ : "cc" \
349 #define IRQ_RESTORE(x) \
351 __asm__ __volatile__( \
352 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
356 #define IRQ_GETSTATE() \
359 __asm__ __volatile__( \
360 "in %0,__SREG__\n\t" \
361 : "=r" (sreg) /* no inputs & no clobbers */ \
363 (bool)(sreg & 0x80); \
366 typedef uint8_t cpuflags_t;
367 typedef uint8_t cpustack_t;
369 /* Register counts include SREG too */
370 #define CPU_REG_BITS 8
371 #define CPU_REGS_CNT 33
372 #define CPU_SAVED_REGS_CNT 19
373 #define CPU_STACK_GROWS_UPWARD 0
374 #define CPU_SP_ON_EMPTY_SLOT 1
375 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
376 #define CPU_HARVARD 1
379 * Initialization value for registers in stack frame.
380 * The register index is not directly corrispondent to CPU
381 * register numbers. Index 0 is the SREG register: the initial
382 * value is all 0 but the interrupt bit (bit 7).
384 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
387 #error No CPU_... defined.
391 * Execute \a CODE atomically with respect to interrupts.
393 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
395 #define ATOMIC(CODE) \
397 cpuflags_t __flags; \
398 IRQ_SAVE_DISABLE(__flags); \
400 IRQ_RESTORE(__flags); \
404 /// Default for macro not defined in the right arch section
405 #ifndef CPU_REG_INIT_VALUE
406 #define CPU_REG_INIT_VALUE(reg) 0
410 #ifndef CPU_STACK_GROWS_UPWARD
411 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
414 #ifndef CPU_SP_ON_EMPTY_SLOT
415 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
419 * Support stack handling peculiarities of a few CPUs.
421 * Most processors let their stack grow downward and
422 * keep SP pointing at the last pushed value.
424 #if !CPU_STACK_GROWS_UPWARD
425 #if !CPU_SP_ON_EMPTY_SLOT
426 /* Most microprocessors (x86, m68k...) */
427 #define CPU_PUSH_WORD(sp, data) \
428 do { *--(sp) = (data); } while (0)
429 #define CPU_POP_WORD(sp) \
433 #define CPU_PUSH_WORD(sp, data) \
434 do { *(sp)-- = (data); } while (0)
435 #define CPU_POP_WORD(sp) \
439 #else /* CPU_STACK_GROWS_UPWARD */
441 #if !CPU_SP_ON_EMPTY_SLOT
442 /* DSP56K and other weirdos */
443 #define CPU_PUSH_WORD(sp, data) \
444 do { *++(sp) = (cpustack_t)(data); } while (0)
445 #define CPU_POP_WORD(sp) \
448 #error I bet you cannot find a CPU like this
455 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
456 * RTS discards SR while returning (it does not restore it). So we push
457 * 0 to fake the same context.
459 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
461 CPU_PUSH_WORD((sp), (func)); \
462 CPU_PUSH_WORD((sp), 0x100); \
467 * In AVR, the addresses are pushed into the stack as little-endian, while
468 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
469 * no natural endianess).
471 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
473 uint16_t funcaddr = (uint16_t)(func); \
474 CPU_PUSH_WORD((sp), funcaddr); \
475 CPU_PUSH_WORD((sp), funcaddr>>8); \
479 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
480 CPU_PUSH_WORD((sp), (cpustack_t)(func))
485 * \name Default type sizes.
487 * These defaults are reasonable for most 16/32bit machines.
488 * Some of these macros may be overridden by CPU-specific code above.
490 * ANSI C requires that the following equations be true:
492 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
493 * sizeof(float) <= sizeof(double)
494 * CPU_BITS_PER_CHAR >= 8
495 * CPU_BITS_PER_SHORT >= 8
496 * CPU_BITS_PER_INT >= 16
497 * CPU_BITS_PER_LONG >= 32
502 #define SIZEOF_CHAR 1
506 #define SIZEOF_SHORT 2
510 #if CPU_REG_BITS < 32
515 #endif /* !SIZEOF_INT */
518 #if CPU_REG_BITS > 32
519 #define SIZEOF_LONG 8
521 #define SIZEOF_LONG 4
526 #if CPU_REG_BITS < 32
528 #elif CPU_REG_BITS == 32
530 #else /* CPU_REG_BITS > 32 */
535 #ifndef CPU_BITS_PER_CHAR
536 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
539 #ifndef CPU_BITS_PER_SHORT
540 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
543 #ifndef CPU_BITS_PER_INT
544 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
547 #ifndef CPU_BITS_PER_LONG
548 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
551 #ifndef CPU_BITS_PER_PTR
552 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
556 #define BREAKPOINT /* nop */
561 /* Sanity checks for the above definitions */
562 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
563 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
564 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
565 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
566 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
567 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
568 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
569 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
570 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
571 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
572 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
573 #ifdef __HAS_INT64_T__
574 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
575 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
581 * \brief Invoked by the scheduler to stop the CPU when idle.
583 * This hook can be redefined to put the CPU in low-power mode, or to
584 * profile system load with an external strobe, or to save CPU cycles
585 * in hosted environments such as emulators.
588 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
589 /* This emulator hook should yield the CPU to the host. */
591 void emul_idle(void);
593 #define CPU_IDLE emul_idle()
594 #else /* !ARCH_EMUL */
595 #define CPU_IDLE do { /* nothing */ } while (0)
596 #endif /* !ARCH_EMUL */
597 #endif /* !CPU_IDLE */
599 #endif /* DEVLIB_CPU_H */