4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.9 2006/02/23 09:08:43 bernie
21 *#* Add note for a frequently reported non-bug.
23 *#* Revision 1.8 2006/02/10 12:37:45 bernie
24 *#* Add support for ARM on IAR.
26 *#* Revision 1.7 2005/11/27 03:04:38 bernie
27 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
29 *#* Revision 1.6 2005/07/19 07:26:49 bernie
30 *#* Add missing #endif.
32 *#* Revision 1.5 2005/06/27 21:24:17 bernie
33 *#* CPU_CSOURCE(): New macro.
35 *#* Revision 1.4 2005/06/14 06:15:10 bernie
36 *#* Add X86_64 support.
38 *#* Revision 1.3 2005/04/12 04:06:17 bernie
39 *#* Catch missing CPU earlier.
41 *#* Revision 1.2 2005/04/11 19:10:27 bernie
42 *#* Include top-level headers from cfg/ subdir.
44 *#* Revision 1.1 2005/04/11 19:04:13 bernie
45 *#* Move top-level headers to cfg/ subdir.
47 *#* Revision 1.30 2005/03/15 00:20:09 bernie
48 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
50 *#* Revision 1.29 2005/02/16 20:33:24 bernie
51 *#* Preliminary PPC support.
53 *#* Revision 1.28 2004/12/31 17:39:41 bernie
54 *#* Fix documentation.
56 *#* Revision 1.27 2004/12/31 17:02:47 bernie
57 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
59 *#* Revision 1.26 2004/12/13 12:08:12 bernie
60 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
62 *#* Revision 1.25 2004/12/08 08:31:02 bernie
63 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
68 #include <cfg/compiler.h> /* for uintXX_t */
72 * \name Macros for determining CPU endianness.
75 #define CPU_BIG_ENDIAN 0x1234
76 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
79 /*! Macro to include cpu-specific versions of the headers. */
80 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
82 /*! Macro to include cpu-specific versions of implementation files. */
83 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
88 #define NOP nop_instruction()
89 #define IRQ_DISABLE disable_interrupt()
90 #define IRQ_ENABLE enable_interrupt()
92 typedef uint16_t cpuflags_t; // FIXME
93 typedef unsigned int cpustack_t;
95 #define CPU_REG_BITS 16
96 #define CPU_REGS_CNT 16
97 #define CPU_STACK_GROWS_UPWARD 0
98 #define CPU_SP_ON_EMPTY_SLOT 0
99 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
100 #define CPU_HARVARD 0
104 #define NOP asm volatile ("nop")
106 /* Get IRQ_* definitions from the hosting environment. */
109 #define IRQ_DISABLE FIXME
110 #define IRQ_ENABLE FIXME
111 #define IRQ_SAVE_DISABLE(x) FIXME
112 #define IRQ_RESTORE(x) FIXME
113 typedef uint32_t cpuflags_t; // FIXME
114 #endif /* OS_EMBEDDED */
117 #define CPU_REGS_CNT 7
118 #define CPU_STACK_GROWS_UPWARD 0
119 #define CPU_SP_ON_EMPTY_SLOT 0
120 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
121 #define CPU_HARVARD 0
124 typedef uint64_t cpustack_t;
125 #define CPU_REG_BITS 64
128 /* WIN64 is an IL32-P64 weirdo. */
129 #define SIZEOF_LONG 4
132 typedef uint32_t cpustack_t;
133 #define CPU_REG_BITS 32
138 #ifdef __IAR_SYSTEMS_ICC__
142 #define NOP __no_operation()
143 #define IRQ_DISABLE __disable_interrupt()
144 #define IRQ_ENABLE __enable_interrupt()
146 #define IRQ_SAVE_DISABLE(x) \
148 (x) = __get_CPSR(); \
149 __disable_interrupt(); \
152 #define IRQ_RESTORE(x) \
157 #define IRQ_GETSTATE() \
158 ((bool)(__get_CPSR() & 0xb0))
160 #else /* __IAR_SYSTEMS_ICC__ */
162 #warning "IRQ_ macros need testing!"
164 #define NOP asm volatile ("mov r0,r0" ::)
166 #define IRQ_DISABLE \
170 "orr r0, r0, #0xb0\n\t" \
180 "bic r0, r0, #0xb0\n\t" \
186 #define IRQ_SAVE_DISABLE(x) \
191 "orr r0, r0, #0xb0\n\t" \
199 #define IRQ_RESTORE(x) \
210 #define IRQ_GETSTATE() \
220 (bool)(sreg & 0xb0); \
223 #endif /* __IAR_SYSTEMS_ICC_ */
225 typedef uint32_t cpuflags_t;
226 typedef uint32_t cpustack_t;
228 /* Register counts include SREG too */
229 #define CPU_REG_BITS 32
230 #define CPU_REGS_CNT 16
231 #define CPU_SAVED_REGS_CNT FIXME
232 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
233 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
234 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
235 #define CPU_HARVARD 0
238 #define NOP asm volatile ("nop" ::)
240 #define IRQ_DISABLE FIXME
241 #define IRQ_ENABLE FIXME
242 #define IRQ_SAVE_DISABLE(x) FIXME
243 #define IRQ_RESTORE(x) FIXME
244 #define IRQ_GETSTATE() FIXME
246 typedef uint32_t cpuflags_t; // FIXME
247 typedef uint32_t cpustack_t; // FIXME
249 /* Register counts include SREG too */
250 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
251 #define CPU_REGS_CNT FIXME
252 #define CPU_SAVED_REGS_CNT FIXME
253 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
254 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
255 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
256 #define CPU_HARVARD 0
261 #define BREAKPOINT asm(debug)
262 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
263 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
265 #define IRQ_SAVE_DISABLE(x) \
266 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
267 #define IRQ_RESTORE(x) \
268 do { (void)x; asm(move x,SR); } while (0)
270 static inline bool irq_running(void)
272 extern void *user_sp;
275 #define IRQ_RUNNING() irq_running()
277 static inline bool irq_getstate(void)
281 return !(x & 0x0200);
283 #define IRQ_GETSTATE() irq_getstate()
285 typedef uint16_t cpuflags_t;
286 typedef unsigned int cpustack_t;
288 #define CPU_REG_BITS 16
289 #define CPU_REGS_CNT FIXME
290 #define CPU_SAVED_REGS_CNT 8
291 #define CPU_STACK_GROWS_UPWARD 1
292 #define CPU_SP_ON_EMPTY_SLOT 0
293 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
294 #define CPU_HARVARD 1
296 /* Memory is word-addessed in the DSP56K */
297 #define CPU_BITS_PER_CHAR 16
298 #define SIZEOF_SHORT 1
300 #define SIZEOF_LONG 2
305 #define NOP asm volatile ("nop" ::)
306 #define IRQ_DISABLE asm volatile ("cli" ::)
307 #define IRQ_ENABLE asm volatile ("sei" ::)
309 #define IRQ_SAVE_DISABLE(x) \
311 __asm__ __volatile__( \
312 "in %0,__SREG__\n\t" \
314 : "=r" (x) : /* no inputs */ : "cc" \
318 #define IRQ_RESTORE(x) \
320 __asm__ __volatile__( \
321 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
325 #define IRQ_GETSTATE() \
328 __asm__ __volatile__( \
329 "in %0,__SREG__\n\t" \
330 : "=r" (sreg) /* no inputs & no clobbers */ \
332 (bool)(sreg & 0x80); \
335 typedef uint8_t cpuflags_t;
336 typedef uint8_t cpustack_t;
338 /* Register counts include SREG too */
339 #define CPU_REG_BITS 8
340 #define CPU_REGS_CNT 33
341 #define CPU_SAVED_REGS_CNT 19
342 #define CPU_STACK_GROWS_UPWARD 0
343 #define CPU_SP_ON_EMPTY_SLOT 1
344 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
345 #define CPU_HARVARD 1
348 * Initialization value for registers in stack frame.
349 * The register index is not directly corrispondent to CPU
350 * register numbers. Index 0 is the SREG register: the initial
351 * value is all 0 but the interrupt bit (bit 7).
353 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
356 #error No CPU_... defined.
360 * Execute \a CODE atomically with respect to interrupts.
362 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
364 #define ATOMIC(CODE) \
366 cpuflags_t __flags; \
367 IRQ_SAVE_DISABLE(__flags); \
369 IRQ_RESTORE(__flags); \
373 //! Default for macro not defined in the right arch section
374 #ifndef CPU_REG_INIT_VALUE
375 #define CPU_REG_INIT_VALUE(reg) 0
379 #ifndef CPU_STACK_GROWS_UPWARD
380 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
383 #ifndef CPU_SP_ON_EMPTY_SLOT
384 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
388 * Support stack handling peculiarities of a few CPUs.
390 * Most processors let their stack grow downward and
391 * keep SP pointing at the last pushed value.
393 #if !CPU_STACK_GROWS_UPWARD
394 #if !CPU_SP_ON_EMPTY_SLOT
395 /* Most microprocessors (x86, m68k...) */
396 #define CPU_PUSH_WORD(sp, data) \
397 do { *--(sp) = (data); } while (0)
398 #define CPU_POP_WORD(sp) \
402 #define CPU_PUSH_WORD(sp, data) \
403 do { *(sp)-- = (data); } while (0)
404 #define CPU_POP_WORD(sp) \
408 #else /* CPU_STACK_GROWS_UPWARD */
410 #if !CPU_SP_ON_EMPTY_SLOT
411 /* DSP56K and other weirdos */
412 #define CPU_PUSH_WORD(sp, data) \
413 do { *++(sp) = (cpustack_t)(data); } while (0)
414 #define CPU_POP_WORD(sp) \
417 #error I bet you cannot find a CPU like this
424 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
425 * RTS discards SR while returning (it does not restore it). So we push
426 * 0 to fake the same context.
428 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
430 CPU_PUSH_WORD((sp), (func)); \
431 CPU_PUSH_WORD((sp), 0x100); \
436 * In AVR, the addresses are pushed into the stack as little-endian, while
437 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
438 * no natural endianess).
440 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
442 uint16_t funcaddr = (uint16_t)(func); \
443 CPU_PUSH_WORD((sp), funcaddr); \
444 CPU_PUSH_WORD((sp), funcaddr>>8); \
448 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
449 CPU_PUSH_WORD((sp), (func))
454 * \name Default type sizes.
456 * These defaults are reasonable for most 16/32bit machines.
457 * Some of these macros may be overridden by CPU-specific code above.
459 * ANSI C requires that the following equations be true:
461 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
462 * sizeof(float) <= sizeof(double)
463 * CPU_BITS_PER_CHAR >= 8
464 * CPU_BITS_PER_SHORT >= 8
465 * CPU_BITS_PER_INT >= 16
466 * CPU_BITS_PER_LONG >= 32
471 #define SIZEOF_CHAR 1
475 #define SIZEOF_SHORT 2
479 #if CPU_REG_BITS < 32
484 #endif /* !SIZEOF_INT */
487 #if CPU_REG_BITS > 32
488 #define SIZEOF_LONG 8
490 #define SIZEOF_LONG 4
495 #if CPU_REG_BITS < 32
497 #elif CPU_REG_BITS == 32
499 #else /* CPU_REG_BITS > 32 */
504 #ifndef CPU_BITS_PER_CHAR
505 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
508 #ifndef CPU_BITS_PER_SHORT
509 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
512 #ifndef CPU_BITS_PER_INT
513 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
516 #ifndef CPU_BITS_PER_LONG
517 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
520 #ifndef CPU_BITS_PER_PTR
521 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
525 #define BREAKPOINT /* nop */
530 /* Sanity checks for the above definitions */
531 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
532 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
533 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
534 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
535 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
536 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
537 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
538 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
539 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
540 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
541 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
542 #ifdef __HAS_INT64_T__
543 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
544 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
550 * \brief Invoked by the scheduler to stop the CPU when idle.
552 * This hook can be redefined to put the CPU in low-power mode, or to
553 * profile system load with an external strobe, or to save CPU cycles
554 * in hosted environments such as emulators.
557 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
558 /* This emulator hook should yield the CPU to the host. */
560 void SchedulerIdle(void);
562 #define CPU_IDLE SchedulerIdle()
563 #else /* !ARCH_EMUL */
564 #define CPU_IDLE do { /* nothing */ } while (0)
565 #endif /* !ARCH_EMUL */
566 #endif /* !CPU_IDLE */
569 #define SCHEDULER_IDLE CPU_IDLE
571 #endif /* DEVLIB_CPU_H */