4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific definitions
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
43 #include <cfg/compiler.h> /* for uintXX_t */
44 #include <cfg/arch_config.h> /* ARCH_EMUL */
48 * \name Macros for determining CPU endianness.
51 #define CPU_BIG_ENDIAN 0x1234
52 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
55 /** Macro to include cpu-specific versions of the headers. */
56 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
58 /** Macro to include cpu-specific versions of implementation files. */
59 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
64 #define NOP nop_instruction()
65 #define IRQ_DISABLE disable_interrupt()
66 #define IRQ_ENABLE enable_interrupt()
68 typedef uint16_t cpuflags_t; // FIXME
69 typedef unsigned int cpustack_t;
71 #define CPU_REG_BITS 16
72 #define CPU_REGS_CNT 16
73 #define CPU_STACK_GROWS_UPWARD 0
74 #define CPU_SP_ON_EMPTY_SLOT 0
75 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
80 #define NOP asm volatile ("nop")
82 /* Get IRQ_* definitions from the hosting environment. */
85 #define IRQ_DISABLE FIXME
86 #define IRQ_ENABLE FIXME
87 #define IRQ_SAVE_DISABLE(x) FIXME
88 #define IRQ_RESTORE(x) FIXME
89 typedef uint32_t cpuflags_t; // FIXME
90 #endif /* OS_EMBEDDED */
93 #define CPU_REGS_CNT 7
94 #define CPU_SAVED_REGS_CNT 7
95 #define CPU_STACK_GROWS_UPWARD 0
96 #define CPU_SP_ON_EMPTY_SLOT 0
97 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
101 typedef uint64_t cpustack_t;
102 #define CPU_REG_BITS 64
105 /* WIN64 is an IL32-P64 weirdo. */
106 #define SIZEOF_LONG 4
109 typedef uint32_t cpustack_t;
110 #define CPU_REG_BITS 32
115 typedef uint32_t cpuflags_t;
116 typedef uint32_t cpustack_t;
118 /* Register counts include SREG too */
119 #define CPU_REG_BITS 32
120 #define CPU_REGS_CNT 16
121 #define CPU_SAVED_REGS_CNT FIXME
122 #define CPU_STACK_GROWS_UPWARD 0
123 #define CPU_SP_ON_EMPTY_SLOT 0
124 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
125 #define CPU_HARVARD 0
127 #ifdef __IAR_SYSTEMS_ICC__
131 #if __CPU_MODE__ == 1 /* Thumb */
133 extern cpuflags_t get_CPSR(void);
134 extern void set_CPSR(cpuflags_t flags);
136 #define get_CPSR __get_CPSR
137 #define set_CPSR __set_CPSR
140 #define NOP __no_operation()
141 #define IRQ_DISABLE __disable_interrupt()
142 #define IRQ_ENABLE __enable_interrupt()
144 #define IRQ_SAVE_DISABLE(x) \
147 __disable_interrupt(); \
150 #define IRQ_RESTORE(x) \
155 #define IRQ_GETSTATE() \
156 ((bool)(get_CPSR() & 0xb0))
158 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
160 #else /* !__IAR_SYSTEMS_ICC__ */
162 #warning "IRQ_ macros need testing!"
163 #warning "Test now or die :-)"
165 #define NOP asm volatile ("mov r0,r0" ::)
167 #define IRQ_DISABLE \
171 "orr r0, r0, #0xc0\n\t" \
181 "bic r0, r0, #0xc0\n\t" \
187 #define IRQ_SAVE_DISABLE(x) \
191 "orr r0, %0, #0xc0\n\t" \
199 #define IRQ_RESTORE(x) \
208 #define IRQ_GETSTATE() \
216 !((sreg & 0xc0) == 0xc0); \
219 #endif /* !__IAR_SYSTEMS_ICC_ */
222 #define NOP asm volatile ("nop" ::)
224 #define IRQ_DISABLE FIXME
225 #define IRQ_ENABLE FIXME
226 #define IRQ_SAVE_DISABLE(x) FIXME
227 #define IRQ_RESTORE(x) FIXME
228 #define IRQ_GETSTATE() FIXME
230 typedef uint32_t cpuflags_t; // FIXME
231 typedef uint32_t cpustack_t; // FIXME
233 /* Register counts include SREG too */
234 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
235 #define CPU_REGS_CNT FIXME
236 #define CPU_SAVED_REGS_CNT FIXME
237 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
238 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
239 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
240 #define CPU_HARVARD 0
245 #define BREAKPOINT asm(debug)
246 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
247 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
249 #define IRQ_SAVE_DISABLE(x) \
250 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
251 #define IRQ_RESTORE(x) \
252 do { (void)x; asm(move x,SR); } while (0)
254 static inline bool irq_running(void)
256 extern void *user_sp;
259 #define IRQ_RUNNING() irq_running()
261 static inline bool irq_getstate(void)
265 return !(x & 0x0200);
267 #define IRQ_GETSTATE() irq_getstate()
269 typedef uint16_t cpuflags_t;
270 typedef unsigned int cpustack_t;
272 #define CPU_REG_BITS 16
273 #define CPU_REGS_CNT FIXME
274 #define CPU_SAVED_REGS_CNT 8
275 #define CPU_STACK_GROWS_UPWARD 1
276 #define CPU_SP_ON_EMPTY_SLOT 0
277 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
278 #define CPU_HARVARD 1
280 /* Memory is word-addessed in the DSP56K */
281 #define CPU_BITS_PER_CHAR 16
282 #define SIZEOF_SHORT 1
284 #define SIZEOF_LONG 2
289 #define NOP asm volatile ("nop" ::)
290 #define IRQ_DISABLE asm volatile ("cli" ::)
291 #define IRQ_ENABLE asm volatile ("sei" ::)
293 #define IRQ_SAVE_DISABLE(x) \
295 __asm__ __volatile__( \
296 "in %0,__SREG__\n\t" \
298 : "=r" (x) : /* no inputs */ : "cc" \
302 #define IRQ_RESTORE(x) \
304 __asm__ __volatile__( \
305 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
309 #define IRQ_GETSTATE() \
312 __asm__ __volatile__( \
313 "in %0,__SREG__\n\t" \
314 : "=r" (sreg) /* no inputs & no clobbers */ \
316 (bool)(sreg & 0x80); \
319 typedef uint8_t cpuflags_t;
320 typedef uint8_t cpustack_t;
322 /* Register counts include SREG too */
323 #define CPU_REG_BITS 8
324 #define CPU_REGS_CNT 33
325 #define CPU_SAVED_REGS_CNT 19
326 #define CPU_STACK_GROWS_UPWARD 0
327 #define CPU_SP_ON_EMPTY_SLOT 1
328 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
329 #define CPU_HARVARD 1
332 * Initialization value for registers in stack frame.
333 * The register index is not directly corrispondent to CPU
334 * register numbers. Index 0 is the SREG register: the initial
335 * value is all 0 but the interrupt bit (bit 7).
337 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
340 #error No CPU_... defined.
344 * Execute \a CODE atomically with respect to interrupts.
346 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
348 #define ATOMIC(CODE) \
350 cpuflags_t __flags; \
351 IRQ_SAVE_DISABLE(__flags); \
353 IRQ_RESTORE(__flags); \
357 /// Default for macro not defined in the right arch section
358 #ifndef CPU_REG_INIT_VALUE
359 #define CPU_REG_INIT_VALUE(reg) 0
363 #ifndef CPU_STACK_GROWS_UPWARD
364 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
367 #ifndef CPU_SP_ON_EMPTY_SLOT
368 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
372 * Support stack handling peculiarities of a few CPUs.
374 * Most processors let their stack grow downward and
375 * keep SP pointing at the last pushed value.
377 #if !CPU_STACK_GROWS_UPWARD
378 #if !CPU_SP_ON_EMPTY_SLOT
379 /* Most microprocessors (x86, m68k...) */
380 #define CPU_PUSH_WORD(sp, data) \
381 do { *--(sp) = (data); } while (0)
382 #define CPU_POP_WORD(sp) \
386 #define CPU_PUSH_WORD(sp, data) \
387 do { *(sp)-- = (data); } while (0)
388 #define CPU_POP_WORD(sp) \
392 #else /* CPU_STACK_GROWS_UPWARD */
394 #if !CPU_SP_ON_EMPTY_SLOT
395 /* DSP56K and other weirdos */
396 #define CPU_PUSH_WORD(sp, data) \
397 do { *++(sp) = (cpustack_t)(data); } while (0)
398 #define CPU_POP_WORD(sp) \
401 #error I bet you cannot find a CPU like this
408 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
409 * RTS discards SR while returning (it does not restore it). So we push
410 * 0 to fake the same context.
412 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
414 CPU_PUSH_WORD((sp), (func)); \
415 CPU_PUSH_WORD((sp), 0x100); \
420 * In AVR, the addresses are pushed into the stack as little-endian, while
421 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
422 * no natural endianess).
424 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
426 uint16_t funcaddr = (uint16_t)(func); \
427 CPU_PUSH_WORD((sp), funcaddr); \
428 CPU_PUSH_WORD((sp), funcaddr>>8); \
432 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
433 CPU_PUSH_WORD((sp), (cpustack_t)(func))
438 * \name Default type sizes.
440 * These defaults are reasonable for most 16/32bit machines.
441 * Some of these macros may be overridden by CPU-specific code above.
443 * ANSI C requires that the following equations be true:
445 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
446 * sizeof(float) <= sizeof(double)
447 * CPU_BITS_PER_CHAR >= 8
448 * CPU_BITS_PER_SHORT >= 8
449 * CPU_BITS_PER_INT >= 16
450 * CPU_BITS_PER_LONG >= 32
455 #define SIZEOF_CHAR 1
459 #define SIZEOF_SHORT 2
463 #if CPU_REG_BITS < 32
468 #endif /* !SIZEOF_INT */
471 #if CPU_REG_BITS > 32
472 #define SIZEOF_LONG 8
474 #define SIZEOF_LONG 4
479 #if CPU_REG_BITS < 32
481 #elif CPU_REG_BITS == 32
483 #else /* CPU_REG_BITS > 32 */
488 #ifndef CPU_BITS_PER_CHAR
489 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
492 #ifndef CPU_BITS_PER_SHORT
493 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
496 #ifndef CPU_BITS_PER_INT
497 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
500 #ifndef CPU_BITS_PER_LONG
501 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
504 #ifndef CPU_BITS_PER_PTR
505 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
509 #define BREAKPOINT /* nop */
514 /* Sanity checks for the above definitions */
515 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
516 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
517 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
518 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
519 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
520 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
521 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
522 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
523 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
524 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
525 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
526 #ifdef __HAS_INT64_T__
527 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
528 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
534 * \brief Invoked by the scheduler to stop the CPU when idle.
536 * This hook can be redefined to put the CPU in low-power mode, or to
537 * profile system load with an external strobe, or to save CPU cycles
538 * in hosted environments such as emulators.
541 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
542 /* This emulator hook should yield the CPU to the host. */
544 void emul_idle(void);
546 #define CPU_IDLE emul_idle()
547 #else /* !ARCH_EMUL */
548 #define CPU_IDLE do { /* nothing */ } while (0)
549 #endif /* !ARCH_EMUL */
550 #endif /* !CPU_IDLE */
552 #endif /* DEVLIB_CPU_H */