4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.3 2005/04/12 04:06:17 bernie
21 *#* Catch missing CPU earlier.
23 *#* Revision 1.2 2005/04/11 19:10:27 bernie
24 *#* Include top-level headers from cfg/ subdir.
26 *#* Revision 1.1 2005/04/11 19:04:13 bernie
27 *#* Move top-level headers to cfg/ subdir.
29 *#* Revision 1.30 2005/03/15 00:20:09 bernie
30 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
32 *#* Revision 1.29 2005/02/16 20:33:24 bernie
33 *#* Preliminary PPC support.
35 *#* Revision 1.28 2004/12/31 17:39:41 bernie
36 *#* Fix documentation.
38 *#* Revision 1.27 2004/12/31 17:02:47 bernie
39 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
41 *#* Revision 1.26 2004/12/13 12:08:12 bernie
42 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
44 *#* Revision 1.25 2004/12/08 08:31:02 bernie
45 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
50 #include <cfg/compiler.h> /* for uintXX_t */
54 * \name Macros for determining CPU endianness.
57 #define CPU_BIG_ENDIAN 0x1234
58 #define CPU_LITTLE_ENDIAN 0x3412
61 /*! Macro to include cpu-specific versions of the headers. */
62 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
67 #define NOP nop_instruction()
68 #define IRQ_DISABLE disable_interrupt()
69 #define IRQ_ENABLE enable_interrupt()
71 typedef uint16_t cpuflags_t; // FIXME
72 typedef unsigned int cpustack_t;
74 #define CPU_REG_BITS 16
75 #define CPU_REGS_CNT 16
76 #define CPU_STACK_GROWS_UPWARD 0
77 #define CPU_SP_ON_EMPTY_SLOT 0
78 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
83 #define NOP asm volatile ("nop")
84 #define IRQ_DISABLE /* nothing */
85 #define IRQ_ENABLE /* nothing */
86 #define IRQ_SAVE_DISABLE(x) /* nothing */
87 #define IRQ_RESTORE(x) /* nothing */
89 typedef uint32_t cpuflags_t; // FIXME
90 typedef uint32_t cpustack_t;
92 #define CPU_REG_BITS 32
93 #define CPU_REGS_CNT 7
94 #define CPU_STACK_GROWS_UPWARD 0
95 #define CPU_SP_ON_EMPTY_SLOT 0
96 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
100 #define NOP asm volatile ("nop" ::)
101 #define IRQ_DISABLE FIXME
102 #define IRQ_ENABLE FIXME
103 #define IRQ_SAVE_DISABLE(x) FIXME
104 #define IRQ_RESTORE(x) FIXME
105 #define IRQ_GETSTATE() FIXME
107 typedef uint32_t cpuflags_t; // FIXME
108 typedef uint32_t cpustack_t; // FIXME
110 /* Register counts include SREG too */
111 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
112 #define CPU_REGS_CNT FIXME
113 #define CPU_SAVED_REGS_CNT FIXME
114 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
115 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
116 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
117 #define CPU_HARVARD 0
122 #define BREAKPOINT asm(debug)
123 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
124 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
126 #define IRQ_SAVE_DISABLE(x) \
127 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
128 #define IRQ_RESTORE(x) \
129 do { (void)x; asm(move x,SR); } while (0)
131 static inline bool irq_running(void)
133 extern void *user_sp;
136 #define IRQ_RUNNING() irq_running()
138 static inline bool irq_getstate(void)
142 return !(x & 0x0200);
144 #define IRQ_GETSTATE() irq_getstate()
148 typedef uint16_t cpuflags_t;
149 typedef unsigned int cpustack_t;
151 #define CPU_REG_BITS 16
152 #define CPU_REGS_CNT FIXME
153 #define CPU_SAVED_REGS_CNT 8
154 #define CPU_STACK_GROWS_UPWARD 1
155 #define CPU_SP_ON_EMPTY_SLOT 0
156 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
157 #define CPU_HARVARD 1
159 /* Memory is word-addessed in the DSP56K */
160 #define CPU_BITS_PER_CHAR 16
161 #define SIZEOF_SHORT 1
163 #define SIZEOF_LONG 2
168 #define NOP asm volatile ("nop" ::)
169 #define IRQ_DISABLE asm volatile ("cli" ::)
170 #define IRQ_ENABLE asm volatile ("sei" ::)
172 #define IRQ_SAVE_DISABLE(x) \
174 __asm__ __volatile__( \
175 "in %0,__SREG__\n\t" \
177 : "=r" (x) : /* no inputs */ : "cc" \
181 #define IRQ_RESTORE(x) \
183 __asm__ __volatile__( \
184 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
188 #define IRQ_GETSTATE() \
191 __asm__ __volatile__( \
192 "in %0,__SREG__\n\t" \
193 : "=r" (sreg) /* no inputs & no clobbers */ \
195 (bool)(sreg & 0x80); \
198 typedef uint8_t cpuflags_t;
199 typedef uint8_t cpustack_t;
201 /* Register counts include SREG too */
202 #define CPU_REG_BITS 8
203 #define CPU_REGS_CNT 33
204 #define CPU_SAVED_REGS_CNT 19
205 #define CPU_STACK_GROWS_UPWARD 0
206 #define CPU_SP_ON_EMPTY_SLOT 1
207 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
208 #define CPU_HARVARD 1
211 * Initialization value for registers in stack frame.
212 * The register index is not directly corrispondent to CPU
213 * register numbers. Index 0 is the SREG register: the initial
214 * value is all 0 but the interrupt bit (bit 7).
216 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
219 #error No CPU_... defined.
223 * Execute \a CODE atomically with respect to interrupts.
225 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
227 #define ATOMIC(CODE) \
229 cpuflags_t __flags; \
230 IRQ_SAVE_DISABLE(__flags); \
232 IRQ_RESTORE(__flags); \
236 //! Default for macro not defined in the right arch section
237 #ifndef CPU_REG_INIT_VALUE
238 #define CPU_REG_INIT_VALUE(reg) 0
242 #ifndef CPU_STACK_GROWS_UPWARD
243 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
246 #ifndef CPU_SP_ON_EMPTY_SLOT
247 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
251 * Support stack handling peculiarities of a few CPUs.
253 * Most processors let their stack grow downward and
254 * keep SP pointing at the last pushed value.
256 #if !CPU_STACK_GROWS_UPWARD
257 #if !CPU_SP_ON_EMPTY_SLOT
258 /* Most microprocessors (x86, m68k...) */
259 #define CPU_PUSH_WORD(sp, data) \
260 do { *--(sp) = (data); } while (0)
261 #define CPU_POP_WORD(sp) \
265 #define CPU_PUSH_WORD(sp, data) \
266 do { *(sp)-- = (data); } while (0)
267 #define CPU_POP_WORD(sp) \
271 #else /* CPU_STACK_GROWS_UPWARD */
273 #if !CPU_SP_ON_EMPTY_SLOT
274 /* DSP56K and other weirdos */
275 #define CPU_PUSH_WORD(sp, data) \
276 do { *++(sp) = (cpustack_t)(data); } while (0)
277 #define CPU_POP_WORD(sp) \
280 #error I bet you cannot find a CPU like this
287 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
288 * RTS discards SR while returning (it does not restore it). So we push
289 * 0 to fake the same context.
291 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
293 CPU_PUSH_WORD((sp), (func)); \
294 CPU_PUSH_WORD((sp), 0x100); \
299 * In AVR, the addresses are pushed into the stack as little-endian, while
300 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
301 * no natural endianess).
303 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
305 uint16_t funcaddr = (uint16_t)(func); \
306 CPU_PUSH_WORD((sp), funcaddr); \
307 CPU_PUSH_WORD((sp), funcaddr>>8); \
311 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
312 CPU_PUSH_WORD((sp), (func))
317 * \name Default type sizes.
319 * These defaults are reasonable for most 16/32bit machines.
320 * Some of these macros may be overridden by CPU-specific code above.
322 * ANSI C requires that the following equations be true:
324 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
325 * sizeof(float) <= sizeof(double)
326 * CPU_BITS_PER_CHAR >= 8
327 * CPU_BITS_PER_SHORT >= 8
328 * CPU_BITS_PER_INT >= 16
329 * CPU_BITS_PER_LONG >= 32
334 #define SIZEOF_CHAR 1
338 #define SIZEOF_SHORT 2
342 #if CPU_REG_BITS < 32
347 #endif /* !SIZEOF_INT */
350 #if CPU_REG_BITS > 32
351 #define SIZEOF_LONG 8
353 #define SIZEOF_LONG 4
358 #define SIZEOF_PTR SIZEOF_INT
361 #ifndef CPU_BITS_PER_CHAR
362 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
365 #ifndef CPU_BITS_PER_SHORT
366 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
369 #ifndef CPU_BITS_PER_INT
370 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
373 #ifndef CPU_BITS_PER_LONG
374 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
377 #ifndef CPU_BITS_PER_PTR
378 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
382 #define BREAKPOINT /* nop */
387 /* Sanity checks for the above definitions */
388 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
389 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
390 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
391 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
397 * \brief Invoked by the scheduler to stop the CPU when idle.
399 * This hook can be redefined to put the CPU in low-power mode, or to
400 * profile system load with an external strobe, or to save CPU cycles
401 * in hosted environments such as emulators.
404 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
405 /* This emulator hook should yield the CPU to the host. */
407 void SchedulerIdle(void);
409 #define CPU_IDLE SchedulerIdle()
410 #else /* !ARCH_EMUL */
411 #define CPU_IDLE do { /* nothing */ } while (0)
412 #endif /* !ARCH_EMUL */
413 #endif /* !CPU_IDLE */
416 #define SCHEDULER_IDLE CPU_IDLE
418 #endif /* DEVLIB_CPU_H */