4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.11 2006/03/20 17:49:00 bernie
23 *#* Revision 1.10 2006/02/24 01:17:30 bernie
24 *#* CPU_SAVED_REGS_CNT: Declare for x86/x86_64.
26 *#* Revision 1.9 2006/02/23 09:08:43 bernie
27 *#* Add note for a frequently reported non-bug.
29 *#* Revision 1.8 2006/02/10 12:37:45 bernie
30 *#* Add support for ARM on IAR.
32 *#* Revision 1.7 2005/11/27 03:04:38 bernie
33 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
35 *#* Revision 1.6 2005/07/19 07:26:49 bernie
36 *#* Add missing #endif.
38 *#* Revision 1.5 2005/06/27 21:24:17 bernie
39 *#* CPU_CSOURCE(): New macro.
41 *#* Revision 1.4 2005/06/14 06:15:10 bernie
42 *#* Add X86_64 support.
44 *#* Revision 1.3 2005/04/12 04:06:17 bernie
45 *#* Catch missing CPU earlier.
47 *#* Revision 1.2 2005/04/11 19:10:27 bernie
48 *#* Include top-level headers from cfg/ subdir.
50 *#* Revision 1.1 2005/04/11 19:04:13 bernie
51 *#* Move top-level headers to cfg/ subdir.
53 *#* Revision 1.30 2005/03/15 00:20:09 bernie
54 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
56 *#* Revision 1.29 2005/02/16 20:33:24 bernie
57 *#* Preliminary PPC support.
59 *#* Revision 1.28 2004/12/31 17:39:41 bernie
60 *#* Fix documentation.
62 *#* Revision 1.27 2004/12/31 17:02:47 bernie
63 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
65 *#* Revision 1.26 2004/12/13 12:08:12 bernie
66 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
68 *#* Revision 1.25 2004/12/08 08:31:02 bernie
69 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
74 #include <cfg/compiler.h> /* for uintXX_t */
78 * \name Macros for determining CPU endianness.
81 #define CPU_BIG_ENDIAN 0x1234
82 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
85 /*! Macro to include cpu-specific versions of the headers. */
86 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
88 /*! Macro to include cpu-specific versions of implementation files. */
89 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
94 #define NOP nop_instruction()
95 #define IRQ_DISABLE disable_interrupt()
96 #define IRQ_ENABLE enable_interrupt()
98 typedef uint16_t cpuflags_t; // FIXME
99 typedef unsigned int cpustack_t;
101 #define CPU_REG_BITS 16
102 #define CPU_REGS_CNT 16
103 #define CPU_STACK_GROWS_UPWARD 0
104 #define CPU_SP_ON_EMPTY_SLOT 0
105 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
106 #define CPU_HARVARD 0
110 #define NOP asm volatile ("nop")
112 /* Get IRQ_* definitions from the hosting environment. */
115 #define IRQ_DISABLE FIXME
116 #define IRQ_ENABLE FIXME
117 #define IRQ_SAVE_DISABLE(x) FIXME
118 #define IRQ_RESTORE(x) FIXME
119 typedef uint32_t cpuflags_t; // FIXME
120 #endif /* OS_EMBEDDED */
123 #define CPU_REGS_CNT 7
124 #define CPU_SAVED_REGS_CNT 7
125 #define CPU_STACK_GROWS_UPWARD 0
126 #define CPU_SP_ON_EMPTY_SLOT 0
127 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
128 #define CPU_HARVARD 0
131 typedef uint64_t cpustack_t;
132 #define CPU_REG_BITS 64
135 /* WIN64 is an IL32-P64 weirdo. */
136 #define SIZEOF_LONG 4
139 typedef uint32_t cpustack_t;
140 #define CPU_REG_BITS 32
145 #ifdef __IAR_SYSTEMS_ICC__
149 #define NOP __no_operation()
150 #define IRQ_DISABLE __disable_interrupt()
151 #define IRQ_ENABLE __enable_interrupt()
153 #define IRQ_SAVE_DISABLE(x) \
155 (x) = __get_CPSR(); \
156 __disable_interrupt(); \
159 #define IRQ_RESTORE(x) \
164 #define IRQ_GETSTATE() \
165 ((bool)(__get_CPSR() & 0xb0))
167 #else /* __IAR_SYSTEMS_ICC__ */
169 #warning "IRQ_ macros need testing!"
171 #define NOP asm volatile ("mov r0,r0" ::)
173 #define IRQ_DISABLE \
177 "orr r0, r0, #0xb0\n\t" \
187 "bic r0, r0, #0xb0\n\t" \
193 #define IRQ_SAVE_DISABLE(x) \
198 "orr r0, r0, #0xb0\n\t" \
206 #define IRQ_RESTORE(x) \
217 #define IRQ_GETSTATE() \
227 (bool)(sreg & 0xb0); \
230 #endif /* __IAR_SYSTEMS_ICC_ */
232 typedef uint32_t cpuflags_t;
233 typedef uint32_t cpustack_t;
235 /* Register counts include SREG too */
236 #define CPU_REG_BITS 32
237 #define CPU_REGS_CNT 16
238 #define CPU_SAVED_REGS_CNT FIXME
239 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
240 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
241 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
242 #define CPU_HARVARD 0
245 #define NOP asm volatile ("nop" ::)
247 #define IRQ_DISABLE FIXME
248 #define IRQ_ENABLE FIXME
249 #define IRQ_SAVE_DISABLE(x) FIXME
250 #define IRQ_RESTORE(x) FIXME
251 #define IRQ_GETSTATE() FIXME
253 typedef uint32_t cpuflags_t; // FIXME
254 typedef uint32_t cpustack_t; // FIXME
256 /* Register counts include SREG too */
257 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
258 #define CPU_REGS_CNT FIXME
259 #define CPU_SAVED_REGS_CNT FIXME
260 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
261 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
262 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
263 #define CPU_HARVARD 0
268 #define BREAKPOINT asm(debug)
269 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
270 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
272 #define IRQ_SAVE_DISABLE(x) \
273 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
274 #define IRQ_RESTORE(x) \
275 do { (void)x; asm(move x,SR); } while (0)
277 static inline bool irq_running(void)
279 extern void *user_sp;
282 #define IRQ_RUNNING() irq_running()
284 static inline bool irq_getstate(void)
288 return !(x & 0x0200);
290 #define IRQ_GETSTATE() irq_getstate()
292 typedef uint16_t cpuflags_t;
293 typedef unsigned int cpustack_t;
295 #define CPU_REG_BITS 16
296 #define CPU_REGS_CNT FIXME
297 #define CPU_SAVED_REGS_CNT 8
298 #define CPU_STACK_GROWS_UPWARD 1
299 #define CPU_SP_ON_EMPTY_SLOT 0
300 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
301 #define CPU_HARVARD 1
303 /* Memory is word-addessed in the DSP56K */
304 #define CPU_BITS_PER_CHAR 16
305 #define SIZEOF_SHORT 1
307 #define SIZEOF_LONG 2
312 #define NOP asm volatile ("nop" ::)
313 #define IRQ_DISABLE asm volatile ("cli" ::)
314 #define IRQ_ENABLE asm volatile ("sei" ::)
316 #define IRQ_SAVE_DISABLE(x) \
318 __asm__ __volatile__( \
319 "in %0,__SREG__\n\t" \
321 : "=r" (x) : /* no inputs */ : "cc" \
325 #define IRQ_RESTORE(x) \
327 __asm__ __volatile__( \
328 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
332 #define IRQ_GETSTATE() \
335 __asm__ __volatile__( \
336 "in %0,__SREG__\n\t" \
337 : "=r" (sreg) /* no inputs & no clobbers */ \
339 (bool)(sreg & 0x80); \
342 typedef uint8_t cpuflags_t;
343 typedef uint8_t cpustack_t;
345 /* Register counts include SREG too */
346 #define CPU_REG_BITS 8
347 #define CPU_REGS_CNT 33
348 #define CPU_SAVED_REGS_CNT 19
349 #define CPU_STACK_GROWS_UPWARD 0
350 #define CPU_SP_ON_EMPTY_SLOT 1
351 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
352 #define CPU_HARVARD 1
355 * Initialization value for registers in stack frame.
356 * The register index is not directly corrispondent to CPU
357 * register numbers. Index 0 is the SREG register: the initial
358 * value is all 0 but the interrupt bit (bit 7).
360 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
363 #error No CPU_... defined.
367 * Execute \a CODE atomically with respect to interrupts.
369 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
371 #define ATOMIC(CODE) \
373 cpuflags_t __flags; \
374 IRQ_SAVE_DISABLE(__flags); \
376 IRQ_RESTORE(__flags); \
380 //! Default for macro not defined in the right arch section
381 #ifndef CPU_REG_INIT_VALUE
382 #define CPU_REG_INIT_VALUE(reg) 0
386 #ifndef CPU_STACK_GROWS_UPWARD
387 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
390 #ifndef CPU_SP_ON_EMPTY_SLOT
391 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
395 * Support stack handling peculiarities of a few CPUs.
397 * Most processors let their stack grow downward and
398 * keep SP pointing at the last pushed value.
400 #if !CPU_STACK_GROWS_UPWARD
401 #if !CPU_SP_ON_EMPTY_SLOT
402 /* Most microprocessors (x86, m68k...) */
403 #define CPU_PUSH_WORD(sp, data) \
404 do { *--(sp) = (data); } while (0)
405 #define CPU_POP_WORD(sp) \
409 #define CPU_PUSH_WORD(sp, data) \
410 do { *(sp)-- = (data); } while (0)
411 #define CPU_POP_WORD(sp) \
415 #else /* CPU_STACK_GROWS_UPWARD */
417 #if !CPU_SP_ON_EMPTY_SLOT
418 /* DSP56K and other weirdos */
419 #define CPU_PUSH_WORD(sp, data) \
420 do { *++(sp) = (cpustack_t)(data); } while (0)
421 #define CPU_POP_WORD(sp) \
424 #error I bet you cannot find a CPU like this
431 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
432 * RTS discards SR while returning (it does not restore it). So we push
433 * 0 to fake the same context.
435 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
437 CPU_PUSH_WORD((sp), (func)); \
438 CPU_PUSH_WORD((sp), 0x100); \
443 * In AVR, the addresses are pushed into the stack as little-endian, while
444 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
445 * no natural endianess).
447 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
449 uint16_t funcaddr = (uint16_t)(func); \
450 CPU_PUSH_WORD((sp), funcaddr); \
451 CPU_PUSH_WORD((sp), funcaddr>>8); \
455 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
456 CPU_PUSH_WORD((sp), (cpustack_t)(func))
461 * \name Default type sizes.
463 * These defaults are reasonable for most 16/32bit machines.
464 * Some of these macros may be overridden by CPU-specific code above.
466 * ANSI C requires that the following equations be true:
468 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
469 * sizeof(float) <= sizeof(double)
470 * CPU_BITS_PER_CHAR >= 8
471 * CPU_BITS_PER_SHORT >= 8
472 * CPU_BITS_PER_INT >= 16
473 * CPU_BITS_PER_LONG >= 32
478 #define SIZEOF_CHAR 1
482 #define SIZEOF_SHORT 2
486 #if CPU_REG_BITS < 32
491 #endif /* !SIZEOF_INT */
494 #if CPU_REG_BITS > 32
495 #define SIZEOF_LONG 8
497 #define SIZEOF_LONG 4
502 #if CPU_REG_BITS < 32
504 #elif CPU_REG_BITS == 32
506 #else /* CPU_REG_BITS > 32 */
511 #ifndef CPU_BITS_PER_CHAR
512 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
515 #ifndef CPU_BITS_PER_SHORT
516 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
519 #ifndef CPU_BITS_PER_INT
520 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
523 #ifndef CPU_BITS_PER_LONG
524 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
527 #ifndef CPU_BITS_PER_PTR
528 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
532 #define BREAKPOINT /* nop */
537 /* Sanity checks for the above definitions */
538 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
539 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
540 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
541 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
542 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
543 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
544 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
545 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
546 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
547 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
548 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
549 #ifdef __HAS_INT64_T__
550 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
551 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
557 * \brief Invoked by the scheduler to stop the CPU when idle.
559 * This hook can be redefined to put the CPU in low-power mode, or to
560 * profile system load with an external strobe, or to save CPU cycles
561 * in hosted environments such as emulators.
564 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
565 /* This emulator hook should yield the CPU to the host. */
567 void SchedulerIdle(void);
569 #define CPU_IDLE SchedulerIdle()
570 #else /* !ARCH_EMUL */
571 #define CPU_IDLE do { /* nothing */ } while (0)
572 #endif /* !ARCH_EMUL */
573 #endif /* !CPU_IDLE */
576 #define SCHEDULER_IDLE CPU_IDLE
578 #endif /* DEVLIB_CPU_H */