4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.5 2005/06/27 21:24:17 bernie
21 *#* CPU_CSOURCE(): New macro.
23 *#* Revision 1.4 2005/06/14 06:15:10 bernie
24 *#* Add X86_64 support.
26 *#* Revision 1.3 2005/04/12 04:06:17 bernie
27 *#* Catch missing CPU earlier.
29 *#* Revision 1.2 2005/04/11 19:10:27 bernie
30 *#* Include top-level headers from cfg/ subdir.
32 *#* Revision 1.1 2005/04/11 19:04:13 bernie
33 *#* Move top-level headers to cfg/ subdir.
35 *#* Revision 1.30 2005/03/15 00:20:09 bernie
36 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
38 *#* Revision 1.29 2005/02/16 20:33:24 bernie
39 *#* Preliminary PPC support.
41 *#* Revision 1.28 2004/12/31 17:39:41 bernie
42 *#* Fix documentation.
44 *#* Revision 1.27 2004/12/31 17:02:47 bernie
45 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
47 *#* Revision 1.26 2004/12/13 12:08:12 bernie
48 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
50 *#* Revision 1.25 2004/12/08 08:31:02 bernie
51 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
56 #include <cfg/compiler.h> /* for uintXX_t */
60 * \name Macros for determining CPU endianness.
63 #define CPU_BIG_ENDIAN 0x1234
64 #define CPU_LITTLE_ENDIAN 0x3412
67 /*! Macro to include cpu-specific versions of the headers. */
68 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
70 /*! Macro to include cpu-specific versions of implementation files. */
71 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
76 #define NOP nop_instruction()
77 #define IRQ_DISABLE disable_interrupt()
78 #define IRQ_ENABLE enable_interrupt()
80 typedef uint16_t cpuflags_t; // FIXME
81 typedef unsigned int cpustack_t;
83 #define CPU_REG_BITS 16
84 #define CPU_REGS_CNT 16
85 #define CPU_STACK_GROWS_UPWARD 0
86 #define CPU_SP_ON_EMPTY_SLOT 0
87 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
92 #define NOP asm volatile ("nop")
93 #define IRQ_DISABLE FIXME
94 #define IRQ_ENABLE FIXME
95 #define IRQ_SAVE_DISABLE(x) FIXME
96 #define IRQ_RESTORE(x) FIXME
98 typedef uint32_t cpuflags_t; // FIXME
100 #define CPU_REGS_CNT 7
101 #define CPU_STACK_GROWS_UPWARD 0
102 #define CPU_SP_ON_EMPTY_SLOT 0
103 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
104 #define CPU_HARVARD 0
107 typedef uint64_t cpustack_t;
108 #define CPU_REG_BITS 64
111 /* WIN64 is an IL32-P64 weirdo. */
112 #define SIZEOF_LONG 4
115 typedef uint32_t cpustack_t;
116 #define CPU_REG_BITS 32
120 #define NOP asm volatile ("nop" ::)
121 #define IRQ_DISABLE FIXME
122 #define IRQ_ENABLE FIXME
123 #define IRQ_SAVE_DISABLE(x) FIXME
124 #define IRQ_RESTORE(x) FIXME
125 #define IRQ_GETSTATE() FIXME
127 typedef uint32_t cpuflags_t; // FIXME
128 typedef uint32_t cpustack_t; // FIXME
130 /* Register counts include SREG too */
131 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
132 #define CPU_REGS_CNT FIXME
133 #define CPU_SAVED_REGS_CNT FIXME
134 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
135 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
136 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
137 #define CPU_HARVARD 0
142 #define BREAKPOINT asm(debug)
143 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
144 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
146 #define IRQ_SAVE_DISABLE(x) \
147 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
148 #define IRQ_RESTORE(x) \
149 do { (void)x; asm(move x,SR); } while (0)
151 static inline bool irq_running(void)
153 extern void *user_sp;
156 #define IRQ_RUNNING() irq_running()
158 static inline bool irq_getstate(void)
162 return !(x & 0x0200);
164 #define IRQ_GETSTATE() irq_getstate()
166 typedef uint16_t cpuflags_t;
167 typedef unsigned int cpustack_t;
169 #define CPU_REG_BITS 16
170 #define CPU_REGS_CNT FIXME
171 #define CPU_SAVED_REGS_CNT 8
172 #define CPU_STACK_GROWS_UPWARD 1
173 #define CPU_SP_ON_EMPTY_SLOT 0
174 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
175 #define CPU_HARVARD 1
177 /* Memory is word-addessed in the DSP56K */
178 #define CPU_BITS_PER_CHAR 16
179 #define SIZEOF_SHORT 1
181 #define SIZEOF_LONG 2
186 #define NOP asm volatile ("nop" ::)
187 #define IRQ_DISABLE asm volatile ("cli" ::)
188 #define IRQ_ENABLE asm volatile ("sei" ::)
190 #define IRQ_SAVE_DISABLE(x) \
192 __asm__ __volatile__( \
193 "in %0,__SREG__\n\t" \
195 : "=r" (x) : /* no inputs */ : "cc" \
199 #define IRQ_RESTORE(x) \
201 __asm__ __volatile__( \
202 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
206 #define IRQ_GETSTATE() \
209 __asm__ __volatile__( \
210 "in %0,__SREG__\n\t" \
211 : "=r" (sreg) /* no inputs & no clobbers */ \
213 (bool)(sreg & 0x80); \
216 typedef uint8_t cpuflags_t;
217 typedef uint8_t cpustack_t;
219 /* Register counts include SREG too */
220 #define CPU_REG_BITS 8
221 #define CPU_REGS_CNT 33
222 #define CPU_SAVED_REGS_CNT 19
223 #define CPU_STACK_GROWS_UPWARD 0
224 #define CPU_SP_ON_EMPTY_SLOT 1
225 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
226 #define CPU_HARVARD 1
229 * Initialization value for registers in stack frame.
230 * The register index is not directly corrispondent to CPU
231 * register numbers. Index 0 is the SREG register: the initial
232 * value is all 0 but the interrupt bit (bit 7).
234 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
237 #error No CPU_... defined.
241 * Execute \a CODE atomically with respect to interrupts.
243 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
245 #define ATOMIC(CODE) \
247 cpuflags_t __flags; \
248 IRQ_SAVE_DISABLE(__flags); \
250 IRQ_RESTORE(__flags); \
254 //! Default for macro not defined in the right arch section
255 #ifndef CPU_REG_INIT_VALUE
256 #define CPU_REG_INIT_VALUE(reg) 0
260 #ifndef CPU_STACK_GROWS_UPWARD
261 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
264 #ifndef CPU_SP_ON_EMPTY_SLOT
265 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
269 * Support stack handling peculiarities of a few CPUs.
271 * Most processors let their stack grow downward and
272 * keep SP pointing at the last pushed value.
274 #if !CPU_STACK_GROWS_UPWARD
275 #if !CPU_SP_ON_EMPTY_SLOT
276 /* Most microprocessors (x86, m68k...) */
277 #define CPU_PUSH_WORD(sp, data) \
278 do { *--(sp) = (data); } while (0)
279 #define CPU_POP_WORD(sp) \
283 #define CPU_PUSH_WORD(sp, data) \
284 do { *(sp)-- = (data); } while (0)
285 #define CPU_POP_WORD(sp) \
289 #else /* CPU_STACK_GROWS_UPWARD */
291 #if !CPU_SP_ON_EMPTY_SLOT
292 /* DSP56K and other weirdos */
293 #define CPU_PUSH_WORD(sp, data) \
294 do { *++(sp) = (cpustack_t)(data); } while (0)
295 #define CPU_POP_WORD(sp) \
298 #error I bet you cannot find a CPU like this
305 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
306 * RTS discards SR while returning (it does not restore it). So we push
307 * 0 to fake the same context.
309 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
311 CPU_PUSH_WORD((sp), (func)); \
312 CPU_PUSH_WORD((sp), 0x100); \
317 * In AVR, the addresses are pushed into the stack as little-endian, while
318 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
319 * no natural endianess).
321 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
323 uint16_t funcaddr = (uint16_t)(func); \
324 CPU_PUSH_WORD((sp), funcaddr); \
325 CPU_PUSH_WORD((sp), funcaddr>>8); \
329 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
330 CPU_PUSH_WORD((sp), (func))
335 * \name Default type sizes.
337 * These defaults are reasonable for most 16/32bit machines.
338 * Some of these macros may be overridden by CPU-specific code above.
340 * ANSI C requires that the following equations be true:
342 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
343 * sizeof(float) <= sizeof(double)
344 * CPU_BITS_PER_CHAR >= 8
345 * CPU_BITS_PER_SHORT >= 8
346 * CPU_BITS_PER_INT >= 16
347 * CPU_BITS_PER_LONG >= 32
352 #define SIZEOF_CHAR 1
356 #define SIZEOF_SHORT 2
360 #if CPU_REG_BITS < 32
365 #endif /* !SIZEOF_INT */
368 #if CPU_REG_BITS > 32
369 #define SIZEOF_LONG 8
371 #define SIZEOF_LONG 4
376 #if CPU_REG_BITS < 32
378 #elif CPU_REG_BITS == 32
380 #else /* CPU_REG_BITS > 32 */
384 #ifndef CPU_BITS_PER_CHAR
385 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
388 #ifndef CPU_BITS_PER_SHORT
389 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
392 #ifndef CPU_BITS_PER_INT
393 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
396 #ifndef CPU_BITS_PER_LONG
397 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
400 #ifndef CPU_BITS_PER_PTR
401 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
405 #define BREAKPOINT /* nop */
410 /* Sanity checks for the above definitions */
411 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
412 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
413 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
414 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
415 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
416 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
417 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
418 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
419 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
420 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
421 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
422 #ifdef __HAS_INT64_T__
423 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
424 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
430 * \brief Invoked by the scheduler to stop the CPU when idle.
432 * This hook can be redefined to put the CPU in low-power mode, or to
433 * profile system load with an external strobe, or to save CPU cycles
434 * in hosted environments such as emulators.
437 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
438 /* This emulator hook should yield the CPU to the host. */
440 void SchedulerIdle(void);
442 #define CPU_IDLE SchedulerIdle()
443 #else /* !ARCH_EMUL */
444 #define CPU_IDLE do { /* nothing */ } while (0)
445 #endif /* !ARCH_EMUL */
446 #endif /* !CPU_IDLE */
449 #define SCHEDULER_IDLE CPU_IDLE
451 #endif /* DEVLIB_CPU_H */