4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.4 2005/06/14 06:15:10 bernie
21 *#* Add X86_64 support.
23 *#* Revision 1.3 2005/04/12 04:06:17 bernie
24 *#* Catch missing CPU earlier.
26 *#* Revision 1.2 2005/04/11 19:10:27 bernie
27 *#* Include top-level headers from cfg/ subdir.
29 *#* Revision 1.1 2005/04/11 19:04:13 bernie
30 *#* Move top-level headers to cfg/ subdir.
32 *#* Revision 1.30 2005/03/15 00:20:09 bernie
33 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
35 *#* Revision 1.29 2005/02/16 20:33:24 bernie
36 *#* Preliminary PPC support.
38 *#* Revision 1.28 2004/12/31 17:39:41 bernie
39 *#* Fix documentation.
41 *#* Revision 1.27 2004/12/31 17:02:47 bernie
42 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
44 *#* Revision 1.26 2004/12/13 12:08:12 bernie
45 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
47 *#* Revision 1.25 2004/12/08 08:31:02 bernie
48 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
53 #include <cfg/compiler.h> /* for uintXX_t */
57 * \name Macros for determining CPU endianness.
60 #define CPU_BIG_ENDIAN 0x1234
61 #define CPU_LITTLE_ENDIAN 0x3412
64 /*! Macro to include cpu-specific versions of the headers. */
65 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
70 #define NOP nop_instruction()
71 #define IRQ_DISABLE disable_interrupt()
72 #define IRQ_ENABLE enable_interrupt()
74 typedef uint16_t cpuflags_t; // FIXME
75 typedef unsigned int cpustack_t;
77 #define CPU_REG_BITS 16
78 #define CPU_REGS_CNT 16
79 #define CPU_STACK_GROWS_UPWARD 0
80 #define CPU_SP_ON_EMPTY_SLOT 0
81 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
86 #define NOP asm volatile ("nop")
87 #define IRQ_DISABLE FIXME
88 #define IRQ_ENABLE FIXME
89 #define IRQ_SAVE_DISABLE(x) FIXME
90 #define IRQ_RESTORE(x) FIXME
92 typedef uint32_t cpuflags_t; // FIXME
94 #define CPU_REGS_CNT 7
95 #define CPU_STACK_GROWS_UPWARD 0
96 #define CPU_SP_ON_EMPTY_SLOT 0
97 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
101 typedef uint64_t cpustack_t;
102 #define CPU_REG_BITS 64
105 /* WIN64 is an IL32-P64 weirdo. */
106 #define SIZEOF_LONG 4
109 typedef uint32_t cpustack_t;
110 #define CPU_REG_BITS 32
114 #define NOP asm volatile ("nop" ::)
115 #define IRQ_DISABLE FIXME
116 #define IRQ_ENABLE FIXME
117 #define IRQ_SAVE_DISABLE(x) FIXME
118 #define IRQ_RESTORE(x) FIXME
119 #define IRQ_GETSTATE() FIXME
121 typedef uint32_t cpuflags_t; // FIXME
122 typedef uint32_t cpustack_t; // FIXME
124 /* Register counts include SREG too */
125 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
126 #define CPU_REGS_CNT FIXME
127 #define CPU_SAVED_REGS_CNT FIXME
128 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
129 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
130 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
131 #define CPU_HARVARD 0
136 #define BREAKPOINT asm(debug)
137 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
138 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
140 #define IRQ_SAVE_DISABLE(x) \
141 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
142 #define IRQ_RESTORE(x) \
143 do { (void)x; asm(move x,SR); } while (0)
145 static inline bool irq_running(void)
147 extern void *user_sp;
150 #define IRQ_RUNNING() irq_running()
152 static inline bool irq_getstate(void)
156 return !(x & 0x0200);
158 #define IRQ_GETSTATE() irq_getstate()
162 typedef uint16_t cpuflags_t;
163 typedef unsigned int cpustack_t;
165 #define CPU_REG_BITS 16
166 #define CPU_REGS_CNT FIXME
167 #define CPU_SAVED_REGS_CNT 8
168 #define CPU_STACK_GROWS_UPWARD 1
169 #define CPU_SP_ON_EMPTY_SLOT 0
170 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
171 #define CPU_HARVARD 1
173 /* Memory is word-addessed in the DSP56K */
174 #define CPU_BITS_PER_CHAR 16
175 #define SIZEOF_SHORT 1
177 #define SIZEOF_LONG 2
182 #define NOP asm volatile ("nop" ::)
183 #define IRQ_DISABLE asm volatile ("cli" ::)
184 #define IRQ_ENABLE asm volatile ("sei" ::)
186 #define IRQ_SAVE_DISABLE(x) \
188 __asm__ __volatile__( \
189 "in %0,__SREG__\n\t" \
191 : "=r" (x) : /* no inputs */ : "cc" \
195 #define IRQ_RESTORE(x) \
197 __asm__ __volatile__( \
198 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
202 #define IRQ_GETSTATE() \
205 __asm__ __volatile__( \
206 "in %0,__SREG__\n\t" \
207 : "=r" (sreg) /* no inputs & no clobbers */ \
209 (bool)(sreg & 0x80); \
212 typedef uint8_t cpuflags_t;
213 typedef uint8_t cpustack_t;
215 /* Register counts include SREG too */
216 #define CPU_REG_BITS 8
217 #define CPU_REGS_CNT 33
218 #define CPU_SAVED_REGS_CNT 19
219 #define CPU_STACK_GROWS_UPWARD 0
220 #define CPU_SP_ON_EMPTY_SLOT 1
221 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
222 #define CPU_HARVARD 1
225 * Initialization value for registers in stack frame.
226 * The register index is not directly corrispondent to CPU
227 * register numbers. Index 0 is the SREG register: the initial
228 * value is all 0 but the interrupt bit (bit 7).
230 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
233 #error No CPU_... defined.
237 * Execute \a CODE atomically with respect to interrupts.
239 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
241 #define ATOMIC(CODE) \
243 cpuflags_t __flags; \
244 IRQ_SAVE_DISABLE(__flags); \
246 IRQ_RESTORE(__flags); \
250 //! Default for macro not defined in the right arch section
251 #ifndef CPU_REG_INIT_VALUE
252 #define CPU_REG_INIT_VALUE(reg) 0
256 #ifndef CPU_STACK_GROWS_UPWARD
257 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
260 #ifndef CPU_SP_ON_EMPTY_SLOT
261 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
265 * Support stack handling peculiarities of a few CPUs.
267 * Most processors let their stack grow downward and
268 * keep SP pointing at the last pushed value.
270 #if !CPU_STACK_GROWS_UPWARD
271 #if !CPU_SP_ON_EMPTY_SLOT
272 /* Most microprocessors (x86, m68k...) */
273 #define CPU_PUSH_WORD(sp, data) \
274 do { *--(sp) = (data); } while (0)
275 #define CPU_POP_WORD(sp) \
279 #define CPU_PUSH_WORD(sp, data) \
280 do { *(sp)-- = (data); } while (0)
281 #define CPU_POP_WORD(sp) \
285 #else /* CPU_STACK_GROWS_UPWARD */
287 #if !CPU_SP_ON_EMPTY_SLOT
288 /* DSP56K and other weirdos */
289 #define CPU_PUSH_WORD(sp, data) \
290 do { *++(sp) = (cpustack_t)(data); } while (0)
291 #define CPU_POP_WORD(sp) \
294 #error I bet you cannot find a CPU like this
301 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
302 * RTS discards SR while returning (it does not restore it). So we push
303 * 0 to fake the same context.
305 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
307 CPU_PUSH_WORD((sp), (func)); \
308 CPU_PUSH_WORD((sp), 0x100); \
313 * In AVR, the addresses are pushed into the stack as little-endian, while
314 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
315 * no natural endianess).
317 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
319 uint16_t funcaddr = (uint16_t)(func); \
320 CPU_PUSH_WORD((sp), funcaddr); \
321 CPU_PUSH_WORD((sp), funcaddr>>8); \
325 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
326 CPU_PUSH_WORD((sp), (func))
331 * \name Default type sizes.
333 * These defaults are reasonable for most 16/32bit machines.
334 * Some of these macros may be overridden by CPU-specific code above.
336 * ANSI C requires that the following equations be true:
338 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
339 * sizeof(float) <= sizeof(double)
340 * CPU_BITS_PER_CHAR >= 8
341 * CPU_BITS_PER_SHORT >= 8
342 * CPU_BITS_PER_INT >= 16
343 * CPU_BITS_PER_LONG >= 32
348 #define SIZEOF_CHAR 1
352 #define SIZEOF_SHORT 2
356 #if CPU_REG_BITS < 32
361 #endif /* !SIZEOF_INT */
364 #if CPU_REG_BITS > 32
365 #define SIZEOF_LONG 8
367 #define SIZEOF_LONG 4
372 #if CPU_REG_BITS < 32
374 #elif CPU_REG_BITS == 32
376 #else /* CPU_REG_BITS > 32 */
380 #ifndef CPU_BITS_PER_CHAR
381 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
384 #ifndef CPU_BITS_PER_SHORT
385 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
388 #ifndef CPU_BITS_PER_INT
389 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
392 #ifndef CPU_BITS_PER_LONG
393 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
396 #ifndef CPU_BITS_PER_PTR
397 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
401 #define BREAKPOINT /* nop */
406 /* Sanity checks for the above definitions */
407 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
408 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
409 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
410 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
411 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
412 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
413 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
414 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
415 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
416 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
417 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
418 #ifdef __HAS_INT64_T__
419 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
420 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
426 * \brief Invoked by the scheduler to stop the CPU when idle.
428 * This hook can be redefined to put the CPU in low-power mode, or to
429 * profile system load with an external strobe, or to save CPU cycles
430 * in hosted environments such as emulators.
433 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
434 /* This emulator hook should yield the CPU to the host. */
436 void SchedulerIdle(void);
438 #define CPU_IDLE SchedulerIdle()
439 #else /* !ARCH_EMUL */
440 #define CPU_IDLE do { /* nothing */ } while (0)
441 #endif /* !ARCH_EMUL */
442 #endif /* !CPU_IDLE */
445 #define SCHEDULER_IDLE CPU_IDLE
447 #endif /* DEVLIB_CPU_H */