4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.12 2006/03/21 10:52:39 bernie
21 *#* Update ARM support.
23 *#* Revision 1.11 2006/03/20 17:49:00 bernie
26 *#* Revision 1.10 2006/02/24 01:17:30 bernie
27 *#* CPU_SAVED_REGS_CNT: Declare for x86/x86_64.
29 *#* Revision 1.9 2006/02/23 09:08:43 bernie
30 *#* Add note for a frequently reported non-bug.
32 *#* Revision 1.8 2006/02/10 12:37:45 bernie
33 *#* Add support for ARM on IAR.
35 *#* Revision 1.7 2005/11/27 03:04:38 bernie
36 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
38 *#* Revision 1.6 2005/07/19 07:26:49 bernie
39 *#* Add missing #endif.
41 *#* Revision 1.5 2005/06/27 21:24:17 bernie
42 *#* CPU_CSOURCE(): New macro.
44 *#* Revision 1.4 2005/06/14 06:15:10 bernie
45 *#* Add X86_64 support.
47 *#* Revision 1.3 2005/04/12 04:06:17 bernie
48 *#* Catch missing CPU earlier.
50 *#* Revision 1.2 2005/04/11 19:10:27 bernie
51 *#* Include top-level headers from cfg/ subdir.
53 *#* Revision 1.1 2005/04/11 19:04:13 bernie
54 *#* Move top-level headers to cfg/ subdir.
56 *#* Revision 1.30 2005/03/15 00:20:09 bernie
57 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
59 *#* Revision 1.29 2005/02/16 20:33:24 bernie
60 *#* Preliminary PPC support.
62 *#* Revision 1.28 2004/12/31 17:39:41 bernie
63 *#* Fix documentation.
65 *#* Revision 1.27 2004/12/31 17:02:47 bernie
66 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
68 *#* Revision 1.26 2004/12/13 12:08:12 bernie
69 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
71 *#* Revision 1.25 2004/12/08 08:31:02 bernie
72 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
77 #include <cfg/compiler.h> /* for uintXX_t */
81 * \name Macros for determining CPU endianness.
84 #define CPU_BIG_ENDIAN 0x1234
85 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
88 /*! Macro to include cpu-specific versions of the headers. */
89 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
91 /*! Macro to include cpu-specific versions of implementation files. */
92 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
97 #define NOP nop_instruction()
98 #define IRQ_DISABLE disable_interrupt()
99 #define IRQ_ENABLE enable_interrupt()
101 typedef uint16_t cpuflags_t; // FIXME
102 typedef unsigned int cpustack_t;
104 #define CPU_REG_BITS 16
105 #define CPU_REGS_CNT 16
106 #define CPU_STACK_GROWS_UPWARD 0
107 #define CPU_SP_ON_EMPTY_SLOT 0
108 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
109 #define CPU_HARVARD 0
113 #define NOP asm volatile ("nop")
115 /* Get IRQ_* definitions from the hosting environment. */
118 #define IRQ_DISABLE FIXME
119 #define IRQ_ENABLE FIXME
120 #define IRQ_SAVE_DISABLE(x) FIXME
121 #define IRQ_RESTORE(x) FIXME
122 typedef uint32_t cpuflags_t; // FIXME
123 #endif /* OS_EMBEDDED */
126 #define CPU_REGS_CNT 7
127 #define CPU_SAVED_REGS_CNT 7
128 #define CPU_STACK_GROWS_UPWARD 0
129 #define CPU_SP_ON_EMPTY_SLOT 0
130 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
131 #define CPU_HARVARD 0
134 typedef uint64_t cpustack_t;
135 #define CPU_REG_BITS 64
138 /* WIN64 is an IL32-P64 weirdo. */
139 #define SIZEOF_LONG 4
142 typedef uint32_t cpustack_t;
143 #define CPU_REG_BITS 32
148 typedef uint32_t cpuflags_t;
149 typedef uint32_t cpustack_t;
151 /* Register counts include SREG too */
152 #define CPU_REG_BITS 32
153 #define CPU_REGS_CNT 16
154 #define CPU_SAVED_REGS_CNT FIXME
155 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
156 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
157 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
158 #define CPU_HARVARD 0
160 #ifdef __IAR_SYSTEMS_ICC__
164 #if __CPU_MODE__ == 1 /* Thumb */
166 extern cpuflags_t get_CPSR(void);
167 extern void set_CPSR(cpuflags_t flags);
169 #define get_CPSR __get_CPSR
170 #define set_CPSR __set_CPSR
173 #define NOP __no_operation()
174 #define IRQ_DISABLE __disable_interrupt()
175 #define IRQ_ENABLE __enable_interrupt()
177 #define IRQ_SAVE_DISABLE(x) \
180 __disable_interrupt(); \
183 #define IRQ_RESTORE(x) \
188 #define IRQ_GETSTATE() \
189 ((bool)(get_CPSR() & 0xb0))
191 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
193 #else /* !__IAR_SYSTEMS_ICC__ */
195 #warning "IRQ_ macros need testing!"
197 #define NOP asm volatile ("mov r0,r0" ::)
199 #define IRQ_DISABLE \
203 "orr r0, r0, #0xb0\n\t" \
213 "bic r0, r0, #0xb0\n\t" \
219 #define IRQ_SAVE_DISABLE(x) \
224 "orr r0, r0, #0xb0\n\t" \
232 #define IRQ_RESTORE(x) \
243 #define IRQ_GETSTATE() \
253 (bool)(sreg & 0xb0); \
256 #endif /* __IAR_SYSTEMS_ICC_ */
259 #define NOP asm volatile ("nop" ::)
261 #define IRQ_DISABLE FIXME
262 #define IRQ_ENABLE FIXME
263 #define IRQ_SAVE_DISABLE(x) FIXME
264 #define IRQ_RESTORE(x) FIXME
265 #define IRQ_GETSTATE() FIXME
267 typedef uint32_t cpuflags_t; // FIXME
268 typedef uint32_t cpustack_t; // FIXME
270 /* Register counts include SREG too */
271 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
272 #define CPU_REGS_CNT FIXME
273 #define CPU_SAVED_REGS_CNT FIXME
274 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
275 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
276 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
277 #define CPU_HARVARD 0
282 #define BREAKPOINT asm(debug)
283 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
284 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
286 #define IRQ_SAVE_DISABLE(x) \
287 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
288 #define IRQ_RESTORE(x) \
289 do { (void)x; asm(move x,SR); } while (0)
291 static inline bool irq_running(void)
293 extern void *user_sp;
296 #define IRQ_RUNNING() irq_running()
298 static inline bool irq_getstate(void)
302 return !(x & 0x0200);
304 #define IRQ_GETSTATE() irq_getstate()
306 typedef uint16_t cpuflags_t;
307 typedef unsigned int cpustack_t;
309 #define CPU_REG_BITS 16
310 #define CPU_REGS_CNT FIXME
311 #define CPU_SAVED_REGS_CNT 8
312 #define CPU_STACK_GROWS_UPWARD 1
313 #define CPU_SP_ON_EMPTY_SLOT 0
314 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
315 #define CPU_HARVARD 1
317 /* Memory is word-addessed in the DSP56K */
318 #define CPU_BITS_PER_CHAR 16
319 #define SIZEOF_SHORT 1
321 #define SIZEOF_LONG 2
326 #define NOP asm volatile ("nop" ::)
327 #define IRQ_DISABLE asm volatile ("cli" ::)
328 #define IRQ_ENABLE asm volatile ("sei" ::)
330 #define IRQ_SAVE_DISABLE(x) \
332 __asm__ __volatile__( \
333 "in %0,__SREG__\n\t" \
335 : "=r" (x) : /* no inputs */ : "cc" \
339 #define IRQ_RESTORE(x) \
341 __asm__ __volatile__( \
342 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
346 #define IRQ_GETSTATE() \
349 __asm__ __volatile__( \
350 "in %0,__SREG__\n\t" \
351 : "=r" (sreg) /* no inputs & no clobbers */ \
353 (bool)(sreg & 0x80); \
356 typedef uint8_t cpuflags_t;
357 typedef uint8_t cpustack_t;
359 /* Register counts include SREG too */
360 #define CPU_REG_BITS 8
361 #define CPU_REGS_CNT 33
362 #define CPU_SAVED_REGS_CNT 19
363 #define CPU_STACK_GROWS_UPWARD 0
364 #define CPU_SP_ON_EMPTY_SLOT 1
365 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
366 #define CPU_HARVARD 1
369 * Initialization value for registers in stack frame.
370 * The register index is not directly corrispondent to CPU
371 * register numbers. Index 0 is the SREG register: the initial
372 * value is all 0 but the interrupt bit (bit 7).
374 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
377 #error No CPU_... defined.
381 * Execute \a CODE atomically with respect to interrupts.
383 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
385 #define ATOMIC(CODE) \
387 cpuflags_t __flags; \
388 IRQ_SAVE_DISABLE(__flags); \
390 IRQ_RESTORE(__flags); \
394 //! Default for macro not defined in the right arch section
395 #ifndef CPU_REG_INIT_VALUE
396 #define CPU_REG_INIT_VALUE(reg) 0
400 #ifndef CPU_STACK_GROWS_UPWARD
401 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
404 #ifndef CPU_SP_ON_EMPTY_SLOT
405 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
409 * Support stack handling peculiarities of a few CPUs.
411 * Most processors let their stack grow downward and
412 * keep SP pointing at the last pushed value.
414 #if !CPU_STACK_GROWS_UPWARD
415 #if !CPU_SP_ON_EMPTY_SLOT
416 /* Most microprocessors (x86, m68k...) */
417 #define CPU_PUSH_WORD(sp, data) \
418 do { *--(sp) = (data); } while (0)
419 #define CPU_POP_WORD(sp) \
423 #define CPU_PUSH_WORD(sp, data) \
424 do { *(sp)-- = (data); } while (0)
425 #define CPU_POP_WORD(sp) \
429 #else /* CPU_STACK_GROWS_UPWARD */
431 #if !CPU_SP_ON_EMPTY_SLOT
432 /* DSP56K and other weirdos */
433 #define CPU_PUSH_WORD(sp, data) \
434 do { *++(sp) = (cpustack_t)(data); } while (0)
435 #define CPU_POP_WORD(sp) \
438 #error I bet you cannot find a CPU like this
445 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
446 * RTS discards SR while returning (it does not restore it). So we push
447 * 0 to fake the same context.
449 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
451 CPU_PUSH_WORD((sp), (func)); \
452 CPU_PUSH_WORD((sp), 0x100); \
457 * In AVR, the addresses are pushed into the stack as little-endian, while
458 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
459 * no natural endianess).
461 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
463 uint16_t funcaddr = (uint16_t)(func); \
464 CPU_PUSH_WORD((sp), funcaddr); \
465 CPU_PUSH_WORD((sp), funcaddr>>8); \
469 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
470 CPU_PUSH_WORD((sp), (cpustack_t)(func))
475 * \name Default type sizes.
477 * These defaults are reasonable for most 16/32bit machines.
478 * Some of these macros may be overridden by CPU-specific code above.
480 * ANSI C requires that the following equations be true:
482 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
483 * sizeof(float) <= sizeof(double)
484 * CPU_BITS_PER_CHAR >= 8
485 * CPU_BITS_PER_SHORT >= 8
486 * CPU_BITS_PER_INT >= 16
487 * CPU_BITS_PER_LONG >= 32
492 #define SIZEOF_CHAR 1
496 #define SIZEOF_SHORT 2
500 #if CPU_REG_BITS < 32
505 #endif /* !SIZEOF_INT */
508 #if CPU_REG_BITS > 32
509 #define SIZEOF_LONG 8
511 #define SIZEOF_LONG 4
516 #if CPU_REG_BITS < 32
518 #elif CPU_REG_BITS == 32
520 #else /* CPU_REG_BITS > 32 */
525 #ifndef CPU_BITS_PER_CHAR
526 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
529 #ifndef CPU_BITS_PER_SHORT
530 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
533 #ifndef CPU_BITS_PER_INT
534 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
537 #ifndef CPU_BITS_PER_LONG
538 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
541 #ifndef CPU_BITS_PER_PTR
542 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
546 #define BREAKPOINT /* nop */
551 /* Sanity checks for the above definitions */
552 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
553 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
554 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
555 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
556 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
557 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
558 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
559 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
560 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
561 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
562 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
563 #ifdef __HAS_INT64_T__
564 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
565 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
571 * \brief Invoked by the scheduler to stop the CPU when idle.
573 * This hook can be redefined to put the CPU in low-power mode, or to
574 * profile system load with an external strobe, or to save CPU cycles
575 * in hosted environments such as emulators.
578 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
579 /* This emulator hook should yield the CPU to the host. */
581 void SchedulerIdle(void);
583 #define CPU_IDLE SchedulerIdle()
584 #else /* !ARCH_EMUL */
585 #define CPU_IDLE do { /* nothing */ } while (0)
586 #endif /* !ARCH_EMUL */
587 #endif /* !CPU_IDLE */
590 #define SCHEDULER_IDLE CPU_IDLE
592 #endif /* DEVLIB_CPU_H */