4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.8 2006/02/10 12:37:45 bernie
21 *#* Add support for ARM on IAR.
23 *#* Revision 1.7 2005/11/27 03:04:38 bernie
24 *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
26 *#* Revision 1.6 2005/07/19 07:26:49 bernie
27 *#* Add missing #endif.
29 *#* Revision 1.5 2005/06/27 21:24:17 bernie
30 *#* CPU_CSOURCE(): New macro.
32 *#* Revision 1.4 2005/06/14 06:15:10 bernie
33 *#* Add X86_64 support.
35 *#* Revision 1.3 2005/04/12 04:06:17 bernie
36 *#* Catch missing CPU earlier.
38 *#* Revision 1.2 2005/04/11 19:10:27 bernie
39 *#* Include top-level headers from cfg/ subdir.
41 *#* Revision 1.1 2005/04/11 19:04:13 bernie
42 *#* Move top-level headers to cfg/ subdir.
44 *#* Revision 1.30 2005/03/15 00:20:09 bernie
45 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
47 *#* Revision 1.29 2005/02/16 20:33:24 bernie
48 *#* Preliminary PPC support.
50 *#* Revision 1.28 2004/12/31 17:39:41 bernie
51 *#* Fix documentation.
53 *#* Revision 1.27 2004/12/31 17:02:47 bernie
54 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
56 *#* Revision 1.26 2004/12/13 12:08:12 bernie
57 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
59 *#* Revision 1.25 2004/12/08 08:31:02 bernie
60 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
65 #include <cfg/compiler.h> /* for uintXX_t */
69 * \name Macros for determining CPU endianness.
72 #define CPU_BIG_ENDIAN 0x1234
73 #define CPU_LITTLE_ENDIAN 0x3412
76 /*! Macro to include cpu-specific versions of the headers. */
77 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
79 /*! Macro to include cpu-specific versions of implementation files. */
80 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
85 #define NOP nop_instruction()
86 #define IRQ_DISABLE disable_interrupt()
87 #define IRQ_ENABLE enable_interrupt()
89 typedef uint16_t cpuflags_t; // FIXME
90 typedef unsigned int cpustack_t;
92 #define CPU_REG_BITS 16
93 #define CPU_REGS_CNT 16
94 #define CPU_STACK_GROWS_UPWARD 0
95 #define CPU_SP_ON_EMPTY_SLOT 0
96 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
101 #define NOP asm volatile ("nop")
103 /* Get IRQ_* definitions from the hosting environment. */
106 #define IRQ_DISABLE FIXME
107 #define IRQ_ENABLE FIXME
108 #define IRQ_SAVE_DISABLE(x) FIXME
109 #define IRQ_RESTORE(x) FIXME
110 typedef uint32_t cpuflags_t; // FIXME
111 #endif /* OS_EMBEDDED */
114 #define CPU_REGS_CNT 7
115 #define CPU_STACK_GROWS_UPWARD 0
116 #define CPU_SP_ON_EMPTY_SLOT 0
117 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
118 #define CPU_HARVARD 0
121 typedef uint64_t cpustack_t;
122 #define CPU_REG_BITS 64
125 /* WIN64 is an IL32-P64 weirdo. */
126 #define SIZEOF_LONG 4
129 typedef uint32_t cpustack_t;
130 #define CPU_REG_BITS 32
135 #ifdef __IAR_SYSTEMS_ICC__
139 #define NOP __no_operation()
140 #define IRQ_DISABLE __disable_interrupt()
141 #define IRQ_ENABLE __enable_interrupt()
143 #define IRQ_SAVE_DISABLE(x) \
145 (x) = __get_CPSR(); \
146 __disable_interrupt(); \
149 #define IRQ_RESTORE(x) \
154 #define IRQ_GETSTATE() \
155 ((bool)(__get_CPSR() & 0xb0))
157 #else /* __IAR_SYSTEMS_ICC__ */
159 #warning "IRQ_ macros need testing!"
161 #define NOP asm volatile ("mov r0,r0" ::)
163 #define IRQ_DISABLE \
167 "orr r0, r0, #0xb0\n\t" \
177 "bic r0, r0, #0xb0\n\t" \
183 #define IRQ_SAVE_DISABLE(x) \
188 "orr r0, r0, #0xb0\n\t" \
196 #define IRQ_RESTORE(x) \
207 #define IRQ_GETSTATE() \
217 (bool)(sreg & 0xb0); \
220 #endif /* __IAR_SYSTEMS_ICC_ */
222 typedef uint32_t cpuflags_t;
223 typedef uint32_t cpustack_t;
225 /* Register counts include SREG too */
226 #define CPU_REG_BITS 32
227 #define CPU_REGS_CNT 16
228 #define CPU_SAVED_REGS_CNT FIXME
229 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
230 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
231 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
232 #define CPU_HARVARD 0
235 #define NOP asm volatile ("nop" ::)
237 #define IRQ_DISABLE FIXME
238 #define IRQ_ENABLE FIXME
239 #define IRQ_SAVE_DISABLE(x) FIXME
240 #define IRQ_RESTORE(x) FIXME
241 #define IRQ_GETSTATE() FIXME
243 typedef uint32_t cpuflags_t; // FIXME
244 typedef uint32_t cpustack_t; // FIXME
246 /* Register counts include SREG too */
247 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
248 #define CPU_REGS_CNT FIXME
249 #define CPU_SAVED_REGS_CNT FIXME
250 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
251 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
252 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
253 #define CPU_HARVARD 0
258 #define BREAKPOINT asm(debug)
259 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
260 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
262 #define IRQ_SAVE_DISABLE(x) \
263 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
264 #define IRQ_RESTORE(x) \
265 do { (void)x; asm(move x,SR); } while (0)
267 static inline bool irq_running(void)
269 extern void *user_sp;
272 #define IRQ_RUNNING() irq_running()
274 static inline bool irq_getstate(void)
278 return !(x & 0x0200);
280 #define IRQ_GETSTATE() irq_getstate()
282 typedef uint16_t cpuflags_t;
283 typedef unsigned int cpustack_t;
285 #define CPU_REG_BITS 16
286 #define CPU_REGS_CNT FIXME
287 #define CPU_SAVED_REGS_CNT 8
288 #define CPU_STACK_GROWS_UPWARD 1
289 #define CPU_SP_ON_EMPTY_SLOT 0
290 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
291 #define CPU_HARVARD 1
293 /* Memory is word-addessed in the DSP56K */
294 #define CPU_BITS_PER_CHAR 16
295 #define SIZEOF_SHORT 1
297 #define SIZEOF_LONG 2
302 #define NOP asm volatile ("nop" ::)
303 #define IRQ_DISABLE asm volatile ("cli" ::)
304 #define IRQ_ENABLE asm volatile ("sei" ::)
306 #define IRQ_SAVE_DISABLE(x) \
308 __asm__ __volatile__( \
309 "in %0,__SREG__\n\t" \
311 : "=r" (x) : /* no inputs */ : "cc" \
315 #define IRQ_RESTORE(x) \
317 __asm__ __volatile__( \
318 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
322 #define IRQ_GETSTATE() \
325 __asm__ __volatile__( \
326 "in %0,__SREG__\n\t" \
327 : "=r" (sreg) /* no inputs & no clobbers */ \
329 (bool)(sreg & 0x80); \
332 typedef uint8_t cpuflags_t;
333 typedef uint8_t cpustack_t;
335 /* Register counts include SREG too */
336 #define CPU_REG_BITS 8
337 #define CPU_REGS_CNT 33
338 #define CPU_SAVED_REGS_CNT 19
339 #define CPU_STACK_GROWS_UPWARD 0
340 #define CPU_SP_ON_EMPTY_SLOT 1
341 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
342 #define CPU_HARVARD 1
345 * Initialization value for registers in stack frame.
346 * The register index is not directly corrispondent to CPU
347 * register numbers. Index 0 is the SREG register: the initial
348 * value is all 0 but the interrupt bit (bit 7).
350 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
353 #error No CPU_... defined.
357 * Execute \a CODE atomically with respect to interrupts.
359 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
361 #define ATOMIC(CODE) \
363 cpuflags_t __flags; \
364 IRQ_SAVE_DISABLE(__flags); \
366 IRQ_RESTORE(__flags); \
370 //! Default for macro not defined in the right arch section
371 #ifndef CPU_REG_INIT_VALUE
372 #define CPU_REG_INIT_VALUE(reg) 0
376 #ifndef CPU_STACK_GROWS_UPWARD
377 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
380 #ifndef CPU_SP_ON_EMPTY_SLOT
381 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
385 * Support stack handling peculiarities of a few CPUs.
387 * Most processors let their stack grow downward and
388 * keep SP pointing at the last pushed value.
390 #if !CPU_STACK_GROWS_UPWARD
391 #if !CPU_SP_ON_EMPTY_SLOT
392 /* Most microprocessors (x86, m68k...) */
393 #define CPU_PUSH_WORD(sp, data) \
394 do { *--(sp) = (data); } while (0)
395 #define CPU_POP_WORD(sp) \
399 #define CPU_PUSH_WORD(sp, data) \
400 do { *(sp)-- = (data); } while (0)
401 #define CPU_POP_WORD(sp) \
405 #else /* CPU_STACK_GROWS_UPWARD */
407 #if !CPU_SP_ON_EMPTY_SLOT
408 /* DSP56K and other weirdos */
409 #define CPU_PUSH_WORD(sp, data) \
410 do { *++(sp) = (cpustack_t)(data); } while (0)
411 #define CPU_POP_WORD(sp) \
414 #error I bet you cannot find a CPU like this
421 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
422 * RTS discards SR while returning (it does not restore it). So we push
423 * 0 to fake the same context.
425 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
427 CPU_PUSH_WORD((sp), (func)); \
428 CPU_PUSH_WORD((sp), 0x100); \
433 * In AVR, the addresses are pushed into the stack as little-endian, while
434 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
435 * no natural endianess).
437 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
439 uint16_t funcaddr = (uint16_t)(func); \
440 CPU_PUSH_WORD((sp), funcaddr); \
441 CPU_PUSH_WORD((sp), funcaddr>>8); \
445 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
446 CPU_PUSH_WORD((sp), (func))
451 * \name Default type sizes.
453 * These defaults are reasonable for most 16/32bit machines.
454 * Some of these macros may be overridden by CPU-specific code above.
456 * ANSI C requires that the following equations be true:
458 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
459 * sizeof(float) <= sizeof(double)
460 * CPU_BITS_PER_CHAR >= 8
461 * CPU_BITS_PER_SHORT >= 8
462 * CPU_BITS_PER_INT >= 16
463 * CPU_BITS_PER_LONG >= 32
468 #define SIZEOF_CHAR 1
472 #define SIZEOF_SHORT 2
476 #if CPU_REG_BITS < 32
481 #endif /* !SIZEOF_INT */
484 #if CPU_REG_BITS > 32
485 #define SIZEOF_LONG 8
487 #define SIZEOF_LONG 4
492 #if CPU_REG_BITS < 32
494 #elif CPU_REG_BITS == 32
496 #else /* CPU_REG_BITS > 32 */
501 #ifndef CPU_BITS_PER_CHAR
502 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
505 #ifndef CPU_BITS_PER_SHORT
506 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
509 #ifndef CPU_BITS_PER_INT
510 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
513 #ifndef CPU_BITS_PER_LONG
514 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
517 #ifndef CPU_BITS_PER_PTR
518 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
522 #define BREAKPOINT /* nop */
527 /* Sanity checks for the above definitions */
528 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
529 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
530 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
531 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
532 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
533 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
534 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
535 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
536 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
537 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
538 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
539 #ifdef __HAS_INT64_T__
540 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
541 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
547 * \brief Invoked by the scheduler to stop the CPU when idle.
549 * This hook can be redefined to put the CPU in low-power mode, or to
550 * profile system load with an external strobe, or to save CPU cycles
551 * in hosted environments such as emulators.
554 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
555 /* This emulator hook should yield the CPU to the host. */
557 void SchedulerIdle(void);
559 #define CPU_IDLE SchedulerIdle()
560 #else /* !ARCH_EMUL */
561 #define CPU_IDLE do { /* nothing */ } while (0)
562 #endif /* !ARCH_EMUL */
563 #endif /* !CPU_IDLE */
566 #define SCHEDULER_IDLE CPU_IDLE
568 #endif /* DEVLIB_CPU_H */