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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Clocking driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cfg/debug.h>
43 /* See: LM3S1968 Microcontroller DATASHEET, p.80 */
44 static const unsigned long xtal_clk[] =
71 /* Extract the main oscillator frequency from the RCC register */
72 #define RCC_TO_CLK(rcc) \
73 (xtal_clk[(((rcc) & SYSCTL_RCC_XTAL_MASK) >> \
74 SYSCTL_RCC_XTAL_SHIFT)])
76 /* Extract the main oscillator frequency from the RCC register */
77 #define RCC_TO_SYSDIV(rcc) \
78 (((rcc & SYSCTL_RCC_SYSDIV_MASK) >> \
79 SYSCTL_RCC_SYSDIV_SHIFT) + 1)
82 * Very small delay: each loop takes 3 cycles.
84 INLINE void __delay(unsigned long iterations)
89 : "=r"(iterations) : : "memory", "cc");
92 unsigned long clock_get_rate(void)
94 unsigned long rcc, clk;
96 rcc = HWREG(SYSCTL_RCC);
98 /* Get the main oscillator frequency */
99 clk = RCC_TO_CLK(rcc);
100 /* Apply system clock divider */
101 clk /= RCC_TO_SYSDIV(rcc);
106 void clock_set_rate(void)
112 rcc = HWREG(SYSCTL_RCC);
113 rcc2 = HWREG(SYSCTL_RCC2);
116 * Step #1: bypass the PLL and system clock divider by setting the
117 * BYPASS bit and clearing the USESYS bit in the RCC register. This
118 * configures the system to run off a “raw” clock source (using the
119 * main oscillator or internal oscillator) and allows for the new PLL
120 * configuration to be validated before switching the system clock to
123 rcc |= SYSCTL_RCC_BYPASS;
124 rcc &= ~SYSCTL_RCC_USESYSDIV;
125 rcc2 |= SYSCTL_RCC2_BYPASS2;
127 /* Write back RCC/RCC2 registers */
128 HWREG(SYSCTL_RCC) = rcc;
129 HWREG(SYSCTL_RCC) = rcc2;
132 * Step #2: select the crystal value (XTAL) and oscillator source
133 * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL
134 * field automatically pulls valid PLL configuration data for the
135 * appropriate crystal, and clearing the PWRDN bit powers and enables
136 * the PLL and its output.
139 /* Enable the main oscillator first. */
140 rcc &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
141 rcc |= SYSCTL_RCC_IOSCDIS;
143 /* Do not override RCC register fields */
144 rcc2 &= ~SYSCTL_RCC2_USERCC2;
146 rcc &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_PWRDN);
147 rcc |= XTAL_FREQ | SYSCTL_RCC_OSCSRC_MAIN;
149 /* Clear the PLL lock interrupt. */
150 HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
152 HWREG(SYSCTL_RCC) = rcc;
157 * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
158 * set the USESYS bit in RCC. The SYSDIV field determines the system
159 * frequency for the microcontroller.
161 rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
164 * Try to evaluate the correct SYSDIV value depending on the desired
167 clk = RCC_TO_CLK(rcc);
168 for (i = 0; i < 16; i++)
176 rcc |= SYSCTL_RCC_USESYSDIV;
177 rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT;
181 * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the
182 * Raw Interrupt Status (RIS) register.
184 for (i = 0; i < 32768; i++)
185 if (HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
189 * Step #5: enable use of the PLL by clearing the BYPASS bit in
192 rcc &= ~SYSCTL_RCC_BYPASS;
194 HWREG(SYSCTL_RCC) = rcc;