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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Clocking driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cfg/debug.h>
41 #include "clock_lm3s.h"
43 /* The PLL VCO frequency is 400 MHz */
44 #define PLL_VCO 400000000UL
46 /* Extract the system clock divisor from the RCC register */
47 #define RCC_TO_DIV(rcc) \
48 (((rcc & SYSCTL_RCC_SYSDIV_MASK) >> \
49 SYSCTL_RCC_SYSDIV_SHIFT) + 1)
52 * Very small delay: each loop takes 3 cycles.
54 INLINE void __delay(unsigned long iterations)
59 : "=r"(iterations) : : "memory", "cc");
62 unsigned long clock_get_rate(void)
64 reg32_t rcc = HWREG(SYSCTL_RCC);
66 return rcc & SYSCTL_RCC_USESYSDIV ?
67 PLL_VCO / 2 / RCC_TO_DIV(rcc) : PLL_VCO;
70 void clock_set_rate(void)
76 rcc = HWREG(SYSCTL_RCC);
77 rcc2 = HWREG(SYSCTL_RCC2);
80 * Step #1: bypass the PLL and system clock divider by setting the
81 * BYPASS bit and clearing the USESYS bit in the RCC register. This
82 * configures the system to run off a “raw” clock source (using the
83 * main oscillator or internal oscillator) and allows for the new PLL
84 * configuration to be validated before switching the system clock to
87 rcc |= SYSCTL_RCC_BYPASS;
88 rcc &= ~SYSCTL_RCC_USESYSDIV;
89 rcc2 |= SYSCTL_RCC2_BYPASS2;
91 /* Write back RCC/RCC2 registers */
92 HWREG(SYSCTL_RCC) = rcc;
93 HWREG(SYSCTL_RCC) = rcc2;
96 * Step #2: select the crystal value (XTAL) and oscillator source
97 * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL
98 * field automatically pulls valid PLL configuration data for the
99 * appropriate crystal, and clearing the PWRDN bit powers and enables
100 * the PLL and its output.
103 /* Enable the main oscillator first. */
104 rcc &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
105 rcc |= SYSCTL_RCC_IOSCDIS;
107 /* Do not override RCC register fields */
108 rcc2 &= ~SYSCTL_RCC2_USERCC2;
110 rcc &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_PWRDN);
111 rcc |= XTAL_FREQ | SYSCTL_RCC_OSCSRC_MAIN;
113 /* Clear the PLL lock interrupt. */
114 HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
116 HWREG(SYSCTL_RCC) = rcc;
117 HWREG(SYSCTL_RCC) = rcc2;
122 * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
123 * set the USESYS bit in RCC. The SYSDIV field determines the system
124 * frequency for the microcontroller.
126 rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
129 * Try to evaluate the correct SYSDIV value depending on the desired
132 * NOTE: with BYPASS=0, SYSDIV < 3 are reserved values (see LM3S1968
133 * Microcontroller DATASHEET, p.78).
136 for (i = 3; i < 16; i++)
137 if (CPU_FREQ >= (clk / (i + 1)))
140 rcc |= SYSCTL_RCC_USESYSDIV | (i << SYSCTL_RCC_SYSDIV_SHIFT);
143 * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the
144 * Raw Interrupt Status (RIS) register.
146 for (i = 0; i < 32768; i++)
147 if (HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
151 * Step #5: enable use of the PLL by clearing the BYPASS bit in
154 rcc &= ~SYSCTL_RCC_BYPASS;
156 HWREG(SYSCTL_RCC) = rcc;