4 * This file is part of BeRTOS.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 Clocking driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cfg/debug.h>
41 #include "clock_stm32.h"
45 INLINE int rcc_get_flag_status(uint32_t flag)
50 /* Get the RCC register index */
52 /* The flag to check is in CR register */
55 /* The flag to check is in BDCR register */
58 /* The flag to check is in CSR register */
61 /* Get the flag position */
62 id = flag & FLAG_MASK;
64 return reg & (1 << id);
67 INLINE uint16_t pll_clock(void)
71 /* Hopefully this is evaluate at compile time... */
72 for (div = 2; div; div--)
73 for (mul = 2; mul <= 16; mul++)
74 if (CPU_FREQ <= (PLL_VCO / div * mul))
76 return mul << 8 | div;
79 INLINE void rcc_pll_config(void)
81 reg32_t reg = RCC->CFGR & CFGR_PLL_MASK;
83 /* Evaluate clock parameters */
84 uint16_t clock = pll_clock();
85 uint32_t pll_mul = ((clock >> 8) - 2) << 18;
86 uint32_t pll_div = ((clock & 0xff) << 1 | 1) << 16;
88 /* Set the PLL configuration bits */
89 reg |= pll_div | pll_mul;
91 /* Store the new value */
98 INLINE void rcc_set_clock_source(uint32_t source)
102 reg = RCC->CFGR & CFGR_SW_MASK;
107 void clock_init(void)
109 /* Initialize global RCC structure */
110 RCC = (struct RCC *)RCC_BASE;
112 /* Enable the internal oscillator */
114 while (!rcc_get_flag_status(RCC_FLAG_HSIRDY));
116 /* Clock the system from internal HSI RC (8 MHz) */
117 rcc_set_clock_source(RCC_SYSCLK_HSI);
119 /* Enable external oscillator */
120 RCC->CR &= CR_HSEON_RESET;
121 RCC->CR &= CR_HSEBYP_RESET;
122 RCC->CR |= CR_HSEON_SET;
123 while (!rcc_get_flag_status(RCC_FLAG_HSERDY));
125 /* Initialize PLL according to CPU_FREQ */
127 while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
129 /* Configure USB clock (48MHz) */
130 *CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
131 /* Configure ADC clock: PCLK2 (9MHz) */
132 RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
133 RCC->CFGR |= RCC_PCLK2_DIV8;
134 /* Configure system clock dividers: PCLK2 (72MHz) */
135 RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
136 RCC->CFGR |= RCC_HCLK_DIV1 << 3;
137 /* Configure system clock dividers: PCLK1 (36MHz) */
138 RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
139 RCC->CFGR |= RCC_HCLK_DIV2;
140 /* Configure system clock dividers: HCLK */
141 RCC->CFGR &= CFGR_HPRE_RESET_MASK;
142 RCC->CFGR |= RCC_SYSCLK_DIV1;
144 /* Set 1 wait state for the flash memory */
145 *(reg32_t *)FLASH_BASE = 0x12;
147 /* Clock the system from the PLL */
148 rcc_set_clock_source(RCC_SYSCLK_PLLCLK);