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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "hsmci_sam3.h"
40 #include <drv/timer.h>
42 #include <drv/irq_cm3.h>
46 /** DMA Transfer Descriptor as well as Linked List Item */
47 typedef struct DmacDesc
49 uint32_t src_addr; /**< Source buffer address */
50 uint32_t dst_addr; /**< Destination buffer address */
51 uint32_t ctrl_a; /**< Control A register settings */
52 uint32_t ctrl_b; /**< Control B register settings */
53 uint32_t dsc_addr; /**< Next descriptor address */
59 #define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1)
61 #define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \
62 BV(HSMCI_SR_RDIRE) | \
63 BV(HSMCI_SR_RCRCE) | \
64 BV(HSMCI_SR_RENDE) | \
66 BV(HSMCI_SR_DCRCE) | \
68 BV(HSMCI_SR_CSTOE) | \
69 BV(HSMCI_SR_BLKOVRE) | \
73 #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
74 | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
76 #define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE))
78 #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
82 } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
85 #define HSMCI_WAIT_DATA_RDY()\
88 } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
90 #define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK)
92 #define HSMCI_HW_INIT() \
94 PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
95 PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
99 #define STROBE_ON() PIOB_SODR = BV(13)
100 #define STROBE_OFF() PIOB_CODR = BV(13)
101 #define STROBE_INIT() \
107 static DECLARE_ISR(hsmci_irq)
109 uint32_t status = HSMCI_SR;
110 if (status & BV(HSMCI_IER_DMADONE))
116 static DECLARE_ISR(dmac_irq)
118 uint32_t stat = DMAC_EBCISR;
120 if (stat & BV(DMAC_EBCISR_ERR3))
122 kprintf("err %08lx\n", stat);
126 void hsmci_readResp(uint32_t *resp, size_t len)
130 for (size_t i = 0; i < len ; i++)
131 resp[i] = HSMCI_RSPR;
134 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
139 HSMCI_ARGR = argument;
140 HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);
142 uint32_t status = HSMCI_SR;
143 while (!(status & BV(HSMCI_SR_CMDRDY)))
145 if (status & HSMCI_RESP_ERROR_MASK)
157 INLINE void hsmci_setBlockSize(size_t blk_size)
159 HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
160 HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
163 void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
166 hsmci_setBlockSize(blk_size);
168 DMAC_CHDR = BV(DMAC_CHDR_DIS0);
170 DMAC_SADDR0 = (uint32_t)buf;
171 DMAC_DADDR0 = (uint32_t)&HSMCI_TDR;
174 DMAC_CFG0 = BV(DMAC_CFG_DST_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
175 DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
176 DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
177 DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
178 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
180 ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
181 DMAC_CHER = BV(DMAC_CHER_ENA0);
185 void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
187 hsmci_setBlockSize(blk_size);
189 DMAC_CHDR = BV(DMAC_CHDR_DIS0);
191 DMAC_SADDR0 = (uint32_t)&HSMCI_RDR;
192 DMAC_DADDR0 = (uint32_t)buf;
195 DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
196 DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
197 DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
198 DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
199 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED | BV(DMAC_CTRLB_IEN));
201 ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
202 DMAC_CHER = BV(DMAC_CHER_ENA0);
206 void hsmci_waitTransfer(void)
208 while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
212 void hsmci_setSpeed(uint32_t data_rate, int flag)
215 HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
217 HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
219 HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
224 void hsmci_init(Hsmci *hsmci)
231 pmc_periphEnable(HSMCI_ID);
232 HSMCI_CR = BV(HSMCI_CR_SWRST);
233 HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
234 HSMCI_IDR = 0xFFFFFFFF;
236 HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
237 HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
238 HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
239 HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
241 sysirq_setHandler(INT_HSMCI, hsmci_irq);
242 HSMCI_CR = BV(HSMCI_CR_MCIEN);
246 DMAC_EBCIDR = 0x3FFFFF;
250 pmc_periphEnable(DMAC_ID);
251 DMAC_EN = BV(DMAC_EN_ENABLE);
252 sysirq_setHandler(INT_DMAC, dmac_irq);
254 DMAC_EBCIER = BV(DMAC_EBCIER_BTC0) | BV(DMAC_EBCIER_ERR0);