4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * GNU General Public License for more details.
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20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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24 * file does not by itself cause the resulting executable to be covered by
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27 * the GNU General Public License.
29 * Copyright 2007,2010 Develer S.r.l. (http://www.develer.com/)
34 * \author Francesco Sacchi <batt@develer.com>
36 * Atmel SAM3 SPI register definitions.
37 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
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57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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70 * For additional information see http://www.ethernut.de/
80 #define SPI0_BASE 0x40008000
82 #define SPI1_BASE 0x4000C000
86 * SPI Control Register
89 #define SPI_CR_OFF 0x00000000 ///< Control register offset.
91 #define SPI_SPIEN 0 ///< SPI enable.
92 #define SPI_SPIDIS 1 ///< SPI disable.
93 #define SPI_SWRST 7 ///< Software reset.
94 #define SPI_LASTXFER 24 ///< Last transfer.
101 #define SPI_MR_OFF 0x00000004 ///< Mode register offset.
103 #define SPI_MSTR 0 ///< Master mode.
104 #define SPI_PS 1 ///< Peripheral select.
105 #define SPI_PCSDEC 2 ///< Chip select decode.
106 #define SPI_FDIV 3 ///< Clock selection.
107 #define SPI_MODFDIS 4 ///< Mode fault detection.
108 #define SPI_LLB 7 ///< Local loopback enable.
109 #define SPI_PCS 0x000F0000 ///< Peripheral chip select mask.
110 #define SPI_PCS_0 0x000E0000 ///< Peripheral chip select 0.
111 #define SPI_PCS_1 0x000D0000 ///< Peripheral chip select 1.
112 #define SPI_PCS_2 0x000B0000 ///< Peripheral chip select 2.
113 #define SPI_PCS_3 0x00070000 ///< Peripheral chip select 3.
114 #define SPI_PCS_SHIFT 16 ///< Least significant bit of peripheral chip select.
115 #define SPI_DLYBCS 0xFF000000 ///< Mask for delay between chip selects.
116 #define SPI_DLYBCS_SHIFT 24 ///< Least significant bit of delay between chip selects.
120 * SPI Receive Data Register
123 #define SPI_RDR_OFF 0x00000008 ///< Receive data register offset.
125 #define SPI_RD 0x0000FFFF ///< Receive data mask.
126 #define SPI_RD_SHIFT 0 ///< Least significant bit of receive data.
130 * SPI Transmit Data Register
133 #define SPI_TDR_OFF 0x0000000C ///< Transmit data register offset.
135 #define SPI_TD 0x0000FFFF ///< Transmit data mask.
136 #define SPI_TD_SHIFT 0 ///< Least significant bit of transmit data.
140 * SPI Status and Interrupt Register
143 #define SPI_SR_OFF 0x00000010 ///< Status register offset.
144 #define SPI_IER_OFF 0x00000014 ///< Interrupt enable register offset.
145 #define SPI_IDR_OFF 0x00000018 ///< Interrupt disable register offset.
146 #define SPI_IMR_OFF 0x0000001C ///< Interrupt mask register offset.
148 #define SPI_RDRF 0 ///< Receive data register full.
149 #define SPI_TDRE 1 ///< Transmit data register empty.
150 #define SPI_MODF 2 ///< Mode fault error.
151 #define SPI_OVRES 3 ///< Overrun error status.
152 #define SPI_ENDRX 4 ///< End of RX buffer.
153 #define SPI_ENDTX 5 ///< End of TX buffer.
154 #define SPI_RXBUFF 6 ///< RX buffer full.
155 #define SPI_TXBUFE 7 ///< TX buffer empty.
156 #define SPI_NSSR 8 ///< NSS rising.
157 #define SPI_TXEMPTY 9 ///< Transmission register empty.
158 #define SPI_SPIENS 16 ///< SPI enable status.
162 * SPI Chip Select Registers
165 #define SPI_CSR0_OFF 0x00000030 ///< Chip select register 0 offset.
166 #define SPI_CSR1_OFF 0x00000034 ///< Chip select register 1 offset.
167 #define SPI_CSR2_OFF 0x00000038 ///< Chip select register 2 offset.
168 #define SPI_CSR3_OFF 0x0000003C ///< Chip select register 3 offset.
170 #define SPI_CPOL 0 ///< Clock polarity.
171 #define SPI_NCPHA 1 ///< Clock phase.
172 #define SPI_CSAAT 3 ///< Chip select active after transfer.
173 #define SPI_BITS 0x000000F0 ///< Bits per transfer mask.
174 #define SPI_BITS_8 0x00000000 ///< 8 bits per transfer.
175 #define SPI_BITS_9 0x00000010 ///< 9 bits per transfer.
176 #define SPI_BITS_10 0x00000020 ///< 10 bits per transfer.
177 #define SPI_BITS_11 0x00000030 ///< 11 bits per transfer.
178 #define SPI_BITS_12 0x00000040 ///< 12 bits per transfer.
179 #define SPI_BITS_13 0x00000050 ///< 13 bits per transfer.
180 #define SPI_BITS_14 0x00000060 ///< 14 bits per transfer.
181 #define SPI_BITS_15 0x00000070 ///< 15 bits per transfer.
182 #define SPI_BITS_16 0x00000080 ///< 16 bits per transfer.
183 #define SPI_BITS_SHIFT 4 ///< Least significant bit of bits per transfer.
184 #define SPI_SCBR 0x0000FF00 ///< Serial clock baud rate mask.
185 #define SPI_SCBR_SHIFT 8 ///< Least significant bit of serial clock baud rate.
186 #define SPI_DLYBS 0x00FF0000 ///< Delay before SPCK mask.
187 #define SPI_DLYBS_SHIFT 16 ///< Least significant bit of delay before SPCK.
188 #define SPI_DLYBCT 0xFF000000 ///< Delay between consecutive transfers mask.
189 #define SPI_DLYBCT_SHIFT 24 ///< Least significant bit of delay between consecutive transfers.
193 * Single SPI Register Addresses
196 #if defined(SPI_BASE)
197 #define SPI0_BASE SPI_BASE
198 #define SPI_CR (*((reg32_t *)(SPI0_BASE + SPI0_CR_OFF))) ///< SPI Control Register Write-only.
199 #define SPI_MR (*((reg32_t *)(SPI0_BASE + SPI0_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0.
200 #define SPI_RDR (*((reg32_t *)(SPI0_BASE + SPI0_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0.
201 #define SPI_TDR (*((reg32_t *)(SPI0_BASE + SPI0_TDR_OFF))) ///< SPI Transmit Data Register Write-only .
202 #define SPI_SR (*((reg32_t *)(SPI0_BASE + SPI0_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0.
203 #define SPI_IER (*((reg32_t *)(SPI0_BASE + SPI0_IER_OFF))) ///< SPI Interrupt Enable Register Write-only.
204 #define SPI_IDR (*((reg32_t *)(SPI0_BASE + SPI0_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only.
205 #define SPI_IMR (*((reg32_t *)(SPI0_BASE + SPI0_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0.
206 #define SPI_CSR0 (*((reg32_t *)(SPI0_BASE + SPI0_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
207 #define SPI_CSR1 (*((reg32_t *)(SPI0_BASE + SPI0_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
208 #define SPI_CSR2 (*((reg32_t *)(SPI0_BASE + SPI0_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
209 #define SPI_CSR3 (*((reg32_t *)(SPI0_BASE + SPI0_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
210 #if defined(SPI_HAS_PDC)
211 #define SPI_RPR (*((reg32_t *)(SPI0_BASE + SPI0_RPR_OFF))) ///< PDC channel 0 receive pointer register.
212 #define SPI_RCR (*((reg32_t *)(SPI0_BASE + SPI0_RCR_OFF))) ///< PDC channel 0 receive counter register.
213 #define SPI_TPR (*((reg32_t *)(SPI0_BASE + SPI0_TPR_OFF))) ///< PDC channel 0 transmit pointer register.
214 #define SPI_TCR (*((reg32_t *)(SPI0_BASE + SPI0_TCR_OFF))) ///< PDC channel 0 transmit counter register.
215 #define SPI_RNPR (*((reg32_t *)(SPI0_BASE + SPI0_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
216 #define SPI_RNCR (*((reg32_t *)(SPI0_BASE + SPI0_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
217 #define SPI_TNPR (*((reg32_t *)(SPI0_BASE + SPI0_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
218 #define SPI_TNCR (*((reg32_t *)(SPI0_BASE + SPI0_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
219 #define SPI_PTCR (*((reg32_t *)(SPI0_BASE + SPI0_PTCR_OFF))) ///< PDC channel 0 transfer control register.
220 #define SPI_PTSR (*((reg32_t *)(SPI0_BASE + SPI0_PTSR_OFF))) ///< PDC channel 0 transfer status register.
221 #endif /* SPI_HAS_PDC */
222 #endif /* SPI_BASE */
226 * SPI 0 Register Addresses
229 #if defined(SPI0_BASE)
230 #define SPI0_CR (*((reg32_t *)(SPI0_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only.
231 #define SPI0_MR (*((reg32_t *)(SPI0_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0.
232 #define SPI0_RDR (*((reg32_t *)(SPI0_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0.
233 #define SPI0_TDR (*((reg32_t *)(SPI0_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only .
234 #define SPI0_SR (*((reg32_t *)(SPI0_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0.
235 #define SPI0_IER (*((reg32_t *)(SPI0_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only.
236 #define SPI0_IDR (*((reg32_t *)(SPI0_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only.
237 #define SPI0_IMR (*((reg32_t *)(SPI0_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0.
238 #define SPI0_CSR0 (*((reg32_t *)(SPI0_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
239 #define SPI0_CSR1 (*((reg32_t *)(SPI0_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
240 #define SPI0_CSR2 (*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
241 #define SPI0_CSR3 (*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
242 #if defined(SPI_HAS_PDC)
243 #define SPI0_RPR (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))) ///< PDC channel 0 receive pointer register.
244 #define SPI0_RCR (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))) ///< PDC channel 0 receive counter register.
245 #define SPI0_TPR (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))) ///< PDC channel 0 transmit pointer register.
246 #define SPI0_TCR (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))) ///< PDC channel 0 transmit counter register.
247 #define SPI0_RNPR (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
248 #define SPI0_RNCR (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
249 #define SPI0_TNPR (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
250 #define SPI0_TNCR (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
251 #define SPI0_PTCR (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
252 #define SPI0_PTSR (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
253 #endif /* SPI_HAS_PDC */
254 #endif /* SPI0_BASE */
258 * SPI 1 Register Addresses
261 #if defined(SPI1_BASE)
262 #define SPI1_CR (*((reg32_t *)(SPI1_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only.
263 #define SPI1_MR (*((reg32_t *)(SPI1_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0.
264 #define SPI1_RDR (*((reg32_t *)(SPI1_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0.
265 #define SPI1_TDR (*((reg32_t *)(SPI1_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only .
266 #define SPI1_SR (*((reg32_t *)(SPI1_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0.
267 #define SPI1_IER (*((reg32_t *)(SPI1_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only.
268 #define SPI1_IDR (*((reg32_t *)(SPI1_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only.
269 #define SPI1_IMR (*((reg32_t *)(SPI1_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0.
270 #define SPI1_CSR0 (*((reg32_t *)(SPI1_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
271 #define SPI1_CSR1 (*((reg32_t *)(SPI1_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
272 #define SPI1_CSR2 (*((reg32_t *)(SPI1_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
273 #define SPI1_CSR3 (*((reg32_t *)(SPI1_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
274 #if defined(SPI_HAS_PDC)
275 #define SPI1_RPR (*((reg32_t *)(SPI1_BASE + PERIPH_RPR_OFF))) ///< PDC channel 1 receive pointer register.
276 #define SPI1_RCR (*((reg32_t *)(SPI1_BASE + PERIPH_RCR_OFF))) ///< PDC channel 1 receive counter register.
277 #define SPI1_TPR (*((reg32_t *)(SPI1_BASE + PERIPH_TPR_OFF))) ///< PDC channel 1 transmit pointer register.
278 #define SPI1_TCR (*((reg32_t *)(SPI1_BASE + PERIPH_TCR_OFF))) ///< PDC channel 1 transmit counter register.
279 #define SPI1_RNPR (*((reg32_t *)(SPI1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
280 #define SPI1_RNCR (*((reg32_t *)(SPI1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
281 #define SPI1_TNPR (*((reg32_t *)(SPI1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
282 #define SPI1_TNCR (*((reg32_t *)(SPI1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
283 #define SPI1_PTCR (*((reg32_t *)(SPI1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
284 #define SPI1_PTSR (*((reg32_t *)(SPI1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
285 #endif /* SPI_HAS_PDC */
286 #endif /* SPI1_BASE */
289 #endif /* SAM3_SPI_H */