4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
38 * \author Daniele Basile <asterix@develer.com>
43 // #include "ser_at91.h"
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
55 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
58 * \name Overridable serial bus hooks
60 * These can be redefined in hw.h to implement
61 * special bus policies such as half-duplex, 485, etc.
65 * TXBEGIN TXCHAR TXEND TXOFF
66 * | __________|__________ | |
69 * ______ __ __ __ __ __ __ ________________
70 * \/ \/ \/ \/ \/ \/ \/
71 * ______/\__/\__/\__/\__/\__/\__/
78 #ifndef SER_UART0_IRQ_INIT
80 * Default IRQ INIT macro - invoked in uart0_init()
82 * - Disable all interrupt
83 * - Register USART0 interrupt
84 * - Enable USART0 clock.
86 #define SER_UART0_IRQ_INIT do { \
87 US0_IDR = 0xFFFFFFFF; \
88 /* Set the vector. */ \
89 AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
90 /* Initialize to edge triggered with defined priority. */ \
91 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
92 /* Enable the USART IRQ */ \
93 AIC_IECR = BV(US0_ID); \
94 PMC_PCER = BV(US0_ID); \
98 #ifndef SER_UART0_BUS_TXINIT
100 * Default TXINIT macro - invoked in uart0_init()
102 * - Disable GPIO on USART0 tx/rx pins
104 * - Set serial param: mode Normal, 8bit data, 1bit stop
105 * - Enable both the receiver and the transmitter
106 * - Enable only the RX complete interrupt
109 #define SER_UART0_BUS_TXINIT do { \
110 PIOA_PDR = BV(5) | BV(6); \
111 US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
112 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
113 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
114 US0_IER = BV(US_RXRDY); \
116 /*#elif Add other ARM families here */
123 #ifndef SER_UART0_BUS_TXBEGIN
125 * Invoked before starting a transmission
127 * - Enable both the receiver and the transmitter
128 * - Enable both the RX complete and TX empty interrupts
130 #define SER_UART0_BUS_TXBEGIN do { \
131 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
132 US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
136 #ifndef SER_UART0_BUS_TXCHAR
138 * Invoked to send one character.
140 #define SER_UART0_BUS_TXCHAR(c) do { \
145 #ifndef SER_UART0_BUS_TXEND
147 * Invoked as soon as the txfifo becomes empty
149 * - Keep both the receiver and the transmitter enabled
150 * - Keep the RX complete interrupt enabled
151 * - Disable the TX empty interrupts
153 #define SER_UART0_BUS_TXEND do { \
154 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
155 US0_IER = BV(US_RXRDY); \
156 US0_IDR = BV(US_TXRDY); \
160 /* End USART0 macros */
162 #ifndef SER_UART1_IRQ_INIT
163 /** \sa SER_UART0_BUS_TXINIT */
164 #define SER_UART1_IRQ_INIT do { \
165 US1_IDR = 0xFFFFFFFF; \
166 /* Set the vector. */ \
167 AIC_SVR(US1_ID) = uart1_irq_dispatcher; \
168 /* Initialize to edge triggered with defined priority. */ \
169 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
170 /* Enable the USART IRQ */ \
171 AIC_IECR = BV(US1_ID); \
172 PMC_PCER = BV(US1_ID); \
176 #ifndef SER_UART1_BUS_TXINIT
177 /** \sa SER_UART1_BUS_TXINIT */
179 #define SER_UART1_BUS_TXINIT do { \
180 PIOA_PDR = BV(21) | BV(22); \
181 US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
182 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
183 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
184 US1_IER = BV(US_RXRDY); \
186 /*#elif Add other ARM families here */
193 #ifndef SER_UART1_BUS_TXBEGIN
194 /** \sa SER_UART1_BUS_TXBEGIN */
195 #define SER_UART1_BUS_TXBEGIN do { \
196 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
197 US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
201 #ifndef SER_UART1_BUS_TXCHAR
202 /** \sa SER_UART1_BUS_TXCHAR */
203 #define SER_UART1_BUS_TXCHAR(c) do { \
208 #ifndef SER_UART1_BUS_TXEND
209 /** \sa SER_UART1_BUS_TXEND */
210 #define SER_UART1_BUS_TXEND do { \
211 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
212 US1_IER = BV(US_RXRDY); \
213 US1_IDR = BV(US_TXRDY); \
218 * \def CONFIG_SER_STROBE
220 * This is a debug facility that can be used to
221 * monitor SER interrupt activity on an external pin.
223 * To use strobes, redefine the macros SER_STROBE_ON,
224 * SER_STROBE_OFF and SER_STROBE_INIT and set
225 * CONFIG_SER_STROBE to 1.
227 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
228 #define SER_STROBE_ON do {/*nop*/} while(0)
229 #define SER_STROBE_OFF do {/*nop*/} while(0)
230 #define SER_STROBE_INIT do {/*nop*/} while(0)
234 /* From the high-level serial driver */
235 extern struct Serial ser_handles[SER_CNT];
237 /* TX and RX buffers */
238 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
239 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
241 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
242 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
245 * Internal hardware state structure
247 * The \a sending variable is true while the transmission
248 * interrupt is retriggering itself.
250 * For the USARTs the \a sending flag is useful for taking specific
251 * actions before sending a burst of data, at the start of a trasmission
252 * but not before every char sent.
254 * For the SPI, this flag is necessary because the SPI sends and receives
255 * bytes at the same time and the SPI IRQ is unique for send/receive.
256 * The only way to start transmission is to write data in SPDR (this
257 * is done by spi_starttx()). We do this *only* if a transfer is
258 * not already started.
262 struct SerialHardware hw;
263 volatile bool sending;
268 * These are to trick GCC into *not* using absolute addressing mode
269 * when accessing ser_handles, which is very expensive.
271 * Accessing through these pointers generates much shorter
272 * (and hopefully faster) code.
274 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
275 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
278 * Serial 0 TX interrupt handler
280 static void uart0_irq_tx(void)
284 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
286 if (fifo_isempty(txfifo))
292 char c = fifo_pop(txfifo);
293 SER_UART0_BUS_TXCHAR(c);
300 * Serial 0 RX complete interrupt handler.
302 static void uart0_irq_rx(void)
306 /* Should be read before US_CRS */
307 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
310 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
312 if (fifo_isfull(rxfifo))
313 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
315 fifo_push(rxfifo, c);
321 * Serial IRQ dispatcher for USART0.
323 static void uart0_irq_dispatcher(void) __attribute__ ((naked));
324 static void uart0_irq_dispatcher(void)
328 if (US0_IMR & BV(US_RXRDY))
331 if (US0_IMR & BV(US_TXRDY))
338 * Serial 1 TX interrupt handler
340 static void uart1_irq_tx(void)
344 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
346 if (fifo_isempty(txfifo))
352 char c = fifo_pop(txfifo);
353 SER_UART1_BUS_TXCHAR(c);
360 * Serial 1 RX complete interrupt handler.
362 static void uart1_irq_rx(void)
366 /* Should be read before US_CRS */
367 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
370 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
372 if (fifo_isfull(rxfifo))
373 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
375 fifo_push(rxfifo, c);
381 * Serial IRQ dispatcher for USART1.
383 static void uart1_irq_dispatcher(void) __attribute__ ((naked));
384 static void uart1_irq_dispatcher(void)
388 if (US1_IMR & BV(US_RXRDY))
391 if (US1_IMR & BV(US_TXRDY))
397 * Callbacks for USART0
399 static void uart0_init(
400 UNUSED_ARG(struct SerialHardware *, _hw),
401 UNUSED_ARG(struct Serial *, ser))
404 SER_UART0_BUS_TXINIT;
408 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
410 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
413 static void uart0_enabletxirq(struct SerialHardware *_hw)
415 struct ArmSerial *hw = (struct ArmSerial *)_hw;
418 * WARNING: racy code here! The tx interrupt sets hw->sending to false
419 * when it runs with an empty fifo. The order of statements in the
425 SER_UART0_BUS_TXBEGIN;
429 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
431 /* Compute baud-rate period */
432 US0_BRGR = CLOCK_FREQ / (16 * rate);
433 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
436 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
438 /* Set UART parity */
441 case SER_PARITY_NONE:
444 US0_MR |= US_PAR_MASK;
447 case SER_PARITY_EVEN:
450 US0_MR |= US_PAR_EVEN;
456 US0_MR |= US_PAR_ODD;
463 * Callbacks for USART1
465 static void uart1_init(
466 UNUSED_ARG(struct SerialHardware *, _hw),
467 UNUSED_ARG(struct Serial *, ser))
470 SER_UART1_BUS_TXINIT;
474 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
476 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
479 static void uart1_enabletxirq(struct SerialHardware *_hw)
481 struct ArmSerial *hw = (struct ArmSerial *)_hw;
484 * WARNING: racy code here! The tx interrupt sets hw->sending to false
485 * when it runs with an empty fifo. The order of statements in the
491 SER_UART1_BUS_TXBEGIN;
495 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
497 /* Compute baud-rate period */
498 US1_BRGR = CLOCK_FREQ / (16 * rate);
499 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
502 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
504 /* Set UART parity */
507 case SER_PARITY_NONE:
510 US1_MR |= US_PAR_MASK;
513 case SER_PARITY_EVEN:
516 US1_MR |= US_PAR_EVEN;
522 US1_MR |= US_PAR_ODD;
529 static bool tx_sending(struct SerialHardware* _hw)
531 struct ArmSerial *hw = (struct ArmSerial *)_hw;
535 // FIXME: move into compiler.h? Ditch?
537 #define C99INIT(name,val) .name = val
538 #elif defined(__GNUC__)
539 #define C99INIT(name,val) name: val
541 #warning No designated initializers, double check your code
542 #define C99INIT(name,val) (val)
546 * High-level interface data structures
548 static const struct SerialHardwareVT UART0_VT =
550 C99INIT(init, uart0_init),
551 C99INIT(cleanup, uart0_cleanup),
552 C99INIT(setBaudrate, uart0_setbaudrate),
553 C99INIT(setParity, uart0_setparity),
554 C99INIT(txStart, uart0_enabletxirq),
555 C99INIT(txSending, tx_sending),
558 static const struct SerialHardwareVT UART1_VT =
560 C99INIT(init, uart1_init),
561 C99INIT(cleanup, uart1_cleanup),
562 C99INIT(setBaudrate, uart1_setbaudrate),
563 C99INIT(setParity, uart1_setparity),
564 C99INIT(txStart, uart1_enabletxirq),
565 C99INIT(txSending, tx_sending),
568 static struct ArmSerial UARTDescs[SER_CNT] =
572 C99INIT(table, &UART0_VT),
573 C99INIT(txbuffer, uart0_txbuffer),
574 C99INIT(rxbuffer, uart0_rxbuffer),
575 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
576 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
578 C99INIT(sending, false),
582 C99INIT(table, &UART1_VT),
583 C99INIT(txbuffer, uart1_txbuffer),
584 C99INIT(rxbuffer, uart1_rxbuffer),
585 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
586 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
588 C99INIT(sending, false),
592 struct SerialHardware *ser_hw_getdesc(int unit)
594 ASSERT(unit < SER_CNT);
595 return &UARTDescs[unit].hw;