4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
38 * \author Daniele Basile <asterix@develer.com>
43 //#include "ser_at91.h"
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
57 * \name Overridable serial bus hooks
59 * These can be redefined in hw.h to implement
60 * special bus policies such as half-duplex, 485, etc.
64 * TXBEGIN TXCHAR TXEND TXOFF
65 * | __________|__________ | |
68 * ______ __ __ __ __ __ __ ________________
69 * \/ \/ \/ \/ \/ \/ \/
70 * ______/\__/\__/\__/\__/\__/\__/
80 * \def CONFIG_SER_STROBE
82 * This is a debug facility that can be used to
83 * monitor SER interrupt activity on an external pin.
85 * To use strobes, redefine the macros SER_STROBE_ON,
86 * SER_STROBE_OFF and SER_STROBE_INIT and set
87 * CONFIG_SER_STROBE to 1.
89 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
90 #define SER_STROBE_ON do {/*nop*/} while(0)
91 #define SER_STROBE_OFF do {/*nop*/} while(0)
92 #define SER_STROBE_INIT do {/*nop*/} while(0)
96 /* From the high-level serial driver */
97 extern struct Serial ser_handles[SER_CNT];
99 /* TX and RX buffers */
100 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
101 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
104 * Internal hardware state structure
106 * The \a sending variable is true while the transmission
107 * interrupt is retriggering itself.
109 * For the USARTs the \a sending flag is useful for taking specific
110 * actions before sending a burst of data, at the start of a trasmission
111 * but not before every char sent.
113 * For the SPI, this flag is necessary because the SPI sends and receives
114 * bytes at the same time and the SPI IRQ is unique for send/receive.
115 * The only way to start transmission is to write data in SPDR (this
116 * is done by spi_starttx()). We do this *only* if a transfer is
117 * not already started.
121 struct SerialHardware hw;
122 volatile bool sending;
127 * These are to trick GCC into *not* using absolute addressing mode
128 * when accessing ser_handles, which is very expensive.
130 * Accessing through these pointers generates much shorter
131 * (and hopefully faster) code.
133 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
136 * Serial 0 TX interrupt handler
138 static void serirq_tx(void)
142 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
144 if (fifo_isempty(txfifo))
146 /* Enable Tx and Rx */
147 US0_CR = BV(US_RXEN) | BV(US_TXEN);
148 /* Enable Rx interrupt */
149 US0_IER = BV(US_RXRDY);
150 /* Disable Tx interrupt */
151 US0_IDR = BV(US_TXRDY);
155 char c = fifo_pop(txfifo);
156 kprintf("Tx char: %c\n", c);
165 * Serial 0 RX complete interrupt handler.
167 static void serirq_rx(void)
171 /* Should be read before US_CRS */
172 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
175 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
177 if (fifo_isfull(rxfifo))
178 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
181 kprintf("Recv char: %c\n", c);
182 fifo_push(rxfifo, c);
189 * Serial IRQ dispatcher.
191 static void serirq_dispatcher(void) __attribute__ ((naked));
192 static void serirq_dispatcher(void)
196 if (US0_IMR & BV(US_RXRDY))
201 if (US0_IMR & BV(US_TXRDY))
212 static void uart0_init(
213 UNUSED_ARG(struct SerialHardware *, _hw),
214 UNUSED_ARG(struct Serial *, ser))
216 /* Disable all interrupt */
217 US0_IDR = 0xFFFFFFFF;
219 /* Set the vector. */
220 AIC_SVR(US0_ID) = serirq_dispatcher;
221 /* Initialize to edge triggered with defined priority. */
222 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
223 /* Enable the USART IRQ */
224 AIC_IECR = BV(US0_ID);
226 /* Enable UART clock. */
227 PMC_PCER = BV(US0_ID);
229 /* Disable GPIO on UART tx/rx pins. */
230 PIOA_PDR = BV(5) | BV(6);
233 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
235 /* Set serial param: mode Normal, 8bit data, 1bit stop */
236 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1;
238 /* Enable Tx and Rx */
239 US0_CR = BV(US_RXEN) | BV(US_TXEN);
241 /* Enable Rx interrupt*/
242 US0_IER = BV(US_RXRDY);
247 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
249 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
252 static void uart0_enabletxirq(struct SerialHardware *_hw)
254 struct ArmSerial *hw = (struct ArmSerial *)_hw;
257 * WARNING: racy code here! The tx interrupt sets hw->sending to false
258 * when it runs with an empty fifo. The order of statements in the
264 /* Enable Tx and Rx */
265 US0_CR = BV(US_RXEN) | BV(US_TXEN);
266 /* Enable Tx and Rx interrupt*/
267 US0_IER = BV(US_TXRDY) | BV(US_RXRDY);
271 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
273 /* Compute baud-rate period */
274 US0_BRGR = CLOCK_FREQ / (16 * rate);
275 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
278 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
280 /* Set UART parity */
283 case SER_PARITY_NONE:
286 US0_MR |= US_PAR_MASK;
289 case SER_PARITY_EVEN:
292 US0_MR |= US_PAR_EVEN;
298 US0_MR |= US_PAR_ODD;
305 static bool tx_sending(struct SerialHardware* _hw)
307 struct ArmSerial *hw = (struct ArmSerial *)_hw;
311 // FIXME: move into compiler.h? Ditch?
313 #define C99INIT(name,val) .name = val
314 #elif defined(__GNUC__)
315 #define C99INIT(name,val) name: val
317 #warning No designated initializers, double check your code
318 #define C99INIT(name,val) (val)
322 * High-level interface data structures
324 static const struct SerialHardwareVT UART0_VT =
326 C99INIT(init, uart0_init),
327 C99INIT(cleanup, uart0_cleanup),
328 C99INIT(setBaudrate, uart0_setbaudrate),
329 C99INIT(setParity, uart0_setparity),
330 C99INIT(txStart, uart0_enabletxirq),
331 C99INIT(txSending, tx_sending),
334 static struct ArmSerial UARTDescs[SER_CNT] =
338 C99INIT(table, &UART0_VT),
339 C99INIT(txbuffer, uart0_txbuffer),
340 C99INIT(rxbuffer, uart0_rxbuffer),
341 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
342 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
344 C99INIT(sending, false),
348 struct SerialHardware *ser_hw_getdesc(int unit)
350 ASSERT(unit < SER_CNT);
351 return &UARTDescs[unit].hw;