4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_at91.c 20881 2008-03-04 14:07:02Z batt $
38 * \author Daniele Basile <asterix@develer.com>
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
55 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
58 * \name Overridable serial bus hooks
60 * These can be redefined in hw.h to implement
61 * special bus policies such as half-duplex, 485, etc.
65 * TXBEGIN TXCHAR TXEND TXOFF
66 * | __________|__________ | |
69 * ______ __ __ __ __ __ __ ________________
70 * \/ \/ \/ \/ \/ \/ \/
71 * ______/\__/\__/\__/\__/\__/\__/
78 #ifndef SER_UART0_BUS_TXINIT
80 * Default TXINIT macro - invoked in uart0_init()
82 * - Disable GPIO on USART0 tx/rx pins
84 #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
85 #warning Check USART0 pins!
87 #define SER_UART0_BUS_TXINIT do { \
88 PIOA_PDR = BV(RXD0) | BV(TXD0); \
93 #ifndef SER_UART0_BUS_TXBEGIN
95 * Invoked before starting a transmission
97 #define SER_UART0_BUS_TXBEGIN
100 #ifndef SER_UART0_BUS_TXCHAR
102 * Invoked to send one character.
104 #define SER_UART0_BUS_TXCHAR(c) do { \
109 #ifndef SER_UART0_BUS_TXEND
111 * Invoked as soon as the txfifo becomes empty
113 #define SER_UART0_BUS_TXEND
116 /* End USART0 macros */
118 #ifndef SER_UART1_BUS_TXINIT
120 * Default TXINIT macro - invoked in uart1_init()
122 * - Disable GPIO on USART1 tx/rx pins
124 #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
125 #warning Check USART1 pins!
127 #define SER_UART1_BUS_TXINIT do { \
128 PIOA_PDR = BV(RXD1) | BV(TXD1); \
133 #ifndef SER_UART1_BUS_TXBEGIN
135 * Invoked before starting a transmission
137 #define SER_UART1_BUS_TXBEGIN
140 #ifndef SER_UART1_BUS_TXCHAR
142 * Invoked to send one character.
144 #define SER_UART1_BUS_TXCHAR(c) do { \
149 #ifndef SER_UART1_BUS_TXEND
151 * Invoked as soon as the txfifo becomes empty
153 #define SER_UART1_BUS_TXEND
157 * \name Overridable SPI hooks
159 * These can be redefined in hw.h to implement
160 * special bus policies such as slave select pin handling, etc.
165 #ifndef SER_SPI0_BUS_TXINIT
167 * Default TXINIT macro - invoked in spi_init()
168 * The default is no action.
170 #define SER_SPI0_BUS_TXINIT
173 #ifndef SER_SPI0_BUS_TXCLOSE
175 * Invoked after the last character has been transmitted.
176 * The default is no action.
178 #define SER_SPI0_BUS_TXCLOSE
181 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
183 #ifndef SER_SPI1_BUS_TXINIT
185 * Default TXINIT macro - invoked in spi_init()
186 * The default is no action.
188 #define SER_SPI1_BUS_TXINIT
191 #ifndef SER_SPI1_BUS_TXCLOSE
193 * Invoked after the last character has been transmitted.
194 * The default is no action.
196 #define SER_SPI1_BUS_TXCLOSE
203 * \def CONFIG_SER_STROBE
205 * This is a debug facility that can be used to
206 * monitor SER interrupt activity on an external pin.
208 * To use strobes, redefine the macros SER_STROBE_ON,
209 * SER_STROBE_OFF and SER_STROBE_INIT and set
210 * CONFIG_SER_STROBE to 1.
212 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
213 #define SER_STROBE_ON do {/*nop*/} while(0)
214 #define SER_STROBE_OFF do {/*nop*/} while(0)
215 #define SER_STROBE_INIT do {/*nop*/} while(0)
219 /* From the high-level serial driver */
220 extern struct Serial ser_handles[SER_CNT];
222 /* TX and RX buffers */
223 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
224 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
226 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
227 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
229 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
230 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
231 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
232 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
233 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
237 * Internal hardware state structure
239 * The \a sending variable is true while the transmission
240 * interrupt is retriggering itself.
242 * For the USARTs the \a sending flag is useful for taking specific
243 * actions before sending a burst of data, at the start of a trasmission
244 * but not before every char sent.
246 * For the SPI, this flag is necessary because the SPI sends and receives
247 * bytes at the same time and the SPI IRQ is unique for send/receive.
248 * The only way to start transmission is to write data in SPDR (this
249 * is done by spi_starttx()). We do this *only* if a transfer is
250 * not already started.
254 struct SerialHardware hw;
255 volatile bool sending;
260 * These are to trick GCC into *not* using absolute addressing mode
261 * when accessing ser_handles, which is very expensive.
263 * Accessing through these pointers generates much shorter
264 * (and hopefully faster) code.
266 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
267 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
269 struct Serial *ser_spi0 = &ser_handles[SER_SPI0];
270 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
271 struct Serial *ser_spi1 = &ser_handles[SER_SPI1];
274 static void uart0_irq_dispatcher(void);
275 static void uart1_irq_dispatcher(void);
276 static void spi0_irq_handler(void);
277 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
278 static void spi1_irq_handler(void);
281 * Callbacks for USART0
283 static void uart0_init(
284 UNUSED_ARG(struct SerialHardware *, _hw),
285 UNUSED_ARG(struct Serial *, ser))
287 US0_IDR = 0xFFFFFFFF;
288 /* Set the vector. */
289 AIC_SVR(US0_ID) = uart0_irq_dispatcher;
290 /* Initialize to edge triggered with defined priority. */
291 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
292 PMC_PCER = BV(US0_ID);
296 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
297 * - Enable both the receiver and the transmitter
298 * - Enable only the RX complete interrupt
300 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
301 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
302 US0_CR = BV(US_RXEN) | BV(US_TXEN);
303 US0_IER = BV(US_RXRDY);
305 SER_UART0_BUS_TXINIT;
307 /* Enable the USART IRQ */
308 AIC_IECR = BV(US0_ID);
313 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
315 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
318 static void uart0_enabletxirq(struct SerialHardware *_hw)
320 struct ArmSerial *hw = (struct ArmSerial *)_hw;
323 * WARNING: racy code here! The tx interrupt sets hw->sending to false
324 * when it runs with an empty fifo. The order of statements in the
331 * - Enable the transmitter
332 * - Enable TX empty interrupt
334 SER_UART0_BUS_TXBEGIN;
335 US0_IER = BV(US_TXEMPTY);
339 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
341 /* Compute baud-rate period */
342 US0_BRGR = CLOCK_FREQ / (16 * rate);
343 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
346 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
348 US0_MR &= ~US_PAR_MASK;
349 /* Set UART parity */
352 case SER_PARITY_NONE:
358 case SER_PARITY_EVEN:
361 US0_MR |= US_PAR_EVEN;
367 US0_MR |= US_PAR_ODD;
376 * Callbacks for USART1
378 static void uart1_init(
379 UNUSED_ARG(struct SerialHardware *, _hw),
380 UNUSED_ARG(struct Serial *, ser))
382 US1_IDR = 0xFFFFFFFF;
383 /* Set the vector. */
384 AIC_SVR(US1_ID) = uart1_irq_dispatcher;
385 /* Initialize to edge triggered with defined priority. */
386 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
387 PMC_PCER = BV(US1_ID);
391 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
392 * - Enable both the receiver and the transmitter
393 * - Enable only the RX complete interrupt
395 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
396 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
397 US1_CR = BV(US_RXEN) | BV(US_TXEN);
398 US1_IER = BV(US_RXRDY);
400 SER_UART1_BUS_TXINIT;
402 /* Enable the USART IRQ */
403 AIC_IECR = BV(US1_ID);
408 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
410 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
413 static void uart1_enabletxirq(struct SerialHardware *_hw)
415 struct ArmSerial *hw = (struct ArmSerial *)_hw;
418 * WARNING: racy code here! The tx interrupt sets hw->sending to false
419 * when it runs with an empty fifo. The order of statements in the
426 * - Enable the transmitter
427 * - Enable TX empty interrupt
429 SER_UART1_BUS_TXBEGIN;
430 US1_IER = BV(US_TXEMPTY);
434 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
436 /* Compute baud-rate period */
437 US1_BRGR = CLOCK_FREQ / (16 * rate);
438 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
441 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
443 US1_MR &= ~US_PAR_MASK;
444 /* Set UART parity */
447 case SER_PARITY_NONE:
453 case SER_PARITY_EVEN:
456 US1_MR |= US_PAR_EVEN;
462 US1_MR |= US_PAR_ODD;
472 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
474 /* Disable PIO on SPI pins */
475 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
478 SPI0_CR = BV(SPI_SWRST);
481 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
482 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
484 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
488 * At reset clock division factor is set to 0, that is
489 * *forbidden*. Set SPI clock to minimum to keep it valid.
491 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
493 /* Disable all irqs */
494 SPI0_IDR = 0xFFFFFFFF;
495 /* Set the vector. */
496 AIC_SVR(SPI0_ID) = spi0_irq_handler;
497 /* Initialize to edge triggered with defined priority. */
498 AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
499 /* Enable the USART IRQ */
500 AIC_IECR = BV(SPI0_ID);
501 PMC_PCER = BV(SPI0_ID);
503 /* Enable interrupt on tx buffer empty */
504 SPI0_IER = BV(SPI_TXEMPTY);
507 SPI0_CR = BV(SPI_SPIEN);
515 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
518 SPI0_CR = BV(SPI_SPIDIS);
520 /* Disable all irqs */
521 SPI0_IDR = 0xFFFFFFFF;
523 SER_SPI0_BUS_TXCLOSE;
525 /* Enable PIO on SPI pins */
526 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
529 static void spi0_starttx(struct SerialHardware *_hw)
531 struct ArmSerial *hw = (struct ArmSerial *)_hw;
534 IRQ_SAVE_DISABLE(flags);
536 /* Send data only if the SPI is not already transmitting */
537 if (!hw->sending && !fifo_isempty(&ser_spi0->txfifo))
540 SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
546 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
548 SPI0_CSR0 &= ~SPI_SCBR;
550 ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
551 SPI0_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
555 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
557 /* Disable PIO on SPI pins */
558 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
561 SPI1_CR = BV(SPI_SWRST);
564 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
565 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
567 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
571 * At reset clock division factor is set to 0, that is
572 * *forbidden*. Set SPI clock to minimum to keep it valid.
574 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
576 /* Disable all irqs */
577 SPI1_IDR = 0xFFFFFFFF;
578 /* Set the vector. */
579 AIC_SVR(SPI1_ID) = spi1_irq_handler;
580 /* Initialize to edge triggered with defined priority. */
581 AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
582 /* Enable the USART IRQ */
583 AIC_IECR = BV(SPI1_ID);
584 PMC_PCER = BV(SPI1_ID);
586 /* Enable interrupt on tx buffer empty */
587 SPI1_IER = BV(SPI_TXEMPTY);
590 SPI1_CR = BV(SPI_SPIEN);
598 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
601 SPI1_CR = BV(SPI_SPIDIS);
603 /* Disable all irqs */
604 SPI1_IDR = 0xFFFFFFFF;
606 SER_SPI1_BUS_TXCLOSE;
608 /* Enable PIO on SPI pins */
609 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
612 static void spi1_starttx(struct SerialHardware *_hw)
614 struct ArmSerial *hw = (struct ArmSerial *)_hw;
617 IRQ_SAVE_DISABLE(flags);
619 /* Send data only if the SPI is not already transmitting */
620 if (!hw->sending && !fifo_isempty(&ser_spi1->txfifo))
623 SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
629 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
631 SPI1_CSR0 &= ~SPI_SCBR;
633 ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
634 SPI1_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
637 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
643 static bool tx_sending(struct SerialHardware* _hw)
645 struct ArmSerial *hw = (struct ArmSerial *)_hw;
649 // FIXME: move into compiler.h? Ditch?
651 #define C99INIT(name,val) .name = val
652 #elif defined(__GNUC__)
653 #define C99INIT(name,val) name: val
655 #warning No designated initializers, double check your code
656 #define C99INIT(name,val) (val)
660 * High-level interface data structures
662 static const struct SerialHardwareVT UART0_VT =
664 C99INIT(init, uart0_init),
665 C99INIT(cleanup, uart0_cleanup),
666 C99INIT(setBaudrate, uart0_setbaudrate),
667 C99INIT(setParity, uart0_setparity),
668 C99INIT(txStart, uart0_enabletxirq),
669 C99INIT(txSending, tx_sending),
672 static const struct SerialHardwareVT UART1_VT =
674 C99INIT(init, uart1_init),
675 C99INIT(cleanup, uart1_cleanup),
676 C99INIT(setBaudrate, uart1_setbaudrate),
677 C99INIT(setParity, uart1_setparity),
678 C99INIT(txStart, uart1_enabletxirq),
679 C99INIT(txSending, tx_sending),
682 static const struct SerialHardwareVT SPI0_VT =
684 C99INIT(init, spi0_init),
685 C99INIT(cleanup, spi0_cleanup),
686 C99INIT(setBaudrate, spi0_setbaudrate),
687 C99INIT(setParity, spi_setparity),
688 C99INIT(txStart, spi0_starttx),
689 C99INIT(txSending, tx_sending),
691 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
692 static const struct SerialHardwareVT SPI1_VT =
694 C99INIT(init, spi1_init),
695 C99INIT(cleanup, spi1_cleanup),
696 C99INIT(setBaudrate, spi1_setbaudrate),
697 C99INIT(setParity, spi_setparity),
698 C99INIT(txStart, spi1_starttx),
699 C99INIT(txSending, tx_sending),
703 static struct ArmSerial UARTDescs[SER_CNT] =
707 C99INIT(table, &UART0_VT),
708 C99INIT(txbuffer, uart0_txbuffer),
709 C99INIT(rxbuffer, uart0_rxbuffer),
710 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
711 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
713 C99INIT(sending, false),
717 C99INIT(table, &UART1_VT),
718 C99INIT(txbuffer, uart1_txbuffer),
719 C99INIT(rxbuffer, uart1_rxbuffer),
720 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
721 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
723 C99INIT(sending, false),
728 C99INIT(table, &SPI0_VT),
729 C99INIT(txbuffer, spi0_txbuffer),
730 C99INIT(rxbuffer, spi0_rxbuffer),
731 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
732 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
734 C99INIT(sending, false),
736 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
739 C99INIT(table, &SPI1_VT),
740 C99INIT(txbuffer, spi1_txbuffer),
741 C99INIT(rxbuffer, spi1_rxbuffer),
742 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
743 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
745 C99INIT(sending, false),
751 struct SerialHardware *ser_hw_getdesc(int unit)
753 ASSERT(unit < SER_CNT);
754 return &UARTDescs[unit].hw;
758 * Serial 0 TX interrupt handler
760 static void uart0_irq_tx(void)
764 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
766 if (fifo_isempty(txfifo))
769 * - Disable the TX empty interrupts
771 US0_IDR = BV(US_TXEMPTY);
773 UARTDescs[SER_UART0].sending = false;
777 char c = fifo_pop(txfifo);
778 SER_UART0_BUS_TXCHAR(c);
785 * Serial 0 RX complete interrupt handler.
787 static void uart0_irq_rx(void)
791 /* Should be read before US_CRS */
792 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
795 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
797 if (fifo_isfull(rxfifo))
798 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
800 fifo_push(rxfifo, c);
806 * Serial IRQ dispatcher for USART0.
808 static void uart0_irq_dispatcher(void) __attribute__ ((interrupt));
809 static void uart0_irq_dispatcher(void)
811 if (US0_CSR & BV(US_RXRDY))
814 if (US0_CSR & BV(US_TXEMPTY))
817 /* Inform hw that we have served the IRQ */
822 * Serial 1 TX interrupt handler
824 static void uart1_irq_tx(void)
828 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
830 if (fifo_isempty(txfifo))
833 * - Disable the TX empty interrupts
835 US1_IDR = BV(US_TXEMPTY);
837 UARTDescs[SER_UART1].sending = false;
841 char c = fifo_pop(txfifo);
842 SER_UART1_BUS_TXCHAR(c);
849 * Serial 1 RX complete interrupt handler.
851 static void uart1_irq_rx(void)
855 /* Should be read before US_CRS */
856 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
859 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
861 if (fifo_isfull(rxfifo))
862 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
864 fifo_push(rxfifo, c);
870 * Serial IRQ dispatcher for USART1.
872 static void uart1_irq_dispatcher(void) __attribute__ ((interrupt));
873 static void uart1_irq_dispatcher(void)
875 if (US1_CSR & BV(US_RXRDY))
878 if (US1_CSR & BV(US_TXEMPTY))
881 /* Inform hw that we have served the IRQ */
886 * SPI0 interrupt handler
888 static void spi0_irq_handler(void) __attribute__ ((interrupt));
889 static void spi0_irq_handler(void)
894 /* Read incoming byte. */
895 if (!fifo_isfull(&ser_spi0->rxfifo))
896 fifo_push(&ser_spi0->rxfifo, c);
900 ser_spi0->status |= SERRF_RXFIFOOVERRUN;
904 if (!fifo_isempty(&ser_spi0->txfifo))
905 SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
907 UARTDescs[SER_SPI0].sending = false;
909 /* Inform hw that we have served the IRQ */
915 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
917 * SPI1 interrupt handler
919 static void spi1_irq_handler(void) __attribute__ ((interrupt));
920 static void spi1_irq_handler(void)
925 /* Read incoming byte. */
926 if (!fifo_isfull(&ser_spi1->rxfifo))
927 fifo_push(&ser_spi1->rxfifo, c);
931 ser_spi1->status |= SERRF_RXFIFOOVERRUN;
935 if (!fifo_isempty(&ser_spi1->txfifo))
936 SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
938 UARTDescs[SER_SPI1].sending = false;
940 /* Inform hw that we have served the IRQ */