4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
38 * \author Daniele Basile <asterix@develer.com>
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
55 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
58 * \name Overridable serial bus hooks
60 * These can be redefined in hw.h to implement
61 * special bus policies such as half-duplex, 485, etc.
65 * TXBEGIN TXCHAR TXEND TXOFF
66 * | __________|__________ | |
69 * ______ __ __ __ __ __ __ ________________
70 * \/ \/ \/ \/ \/ \/ \/
71 * ______/\__/\__/\__/\__/\__/\__/
78 #ifndef SER_UART0_IRQ_INIT
80 * Default IRQ INIT macro - invoked in uart0_init()
82 * - Disable all interrupt
83 * - Register USART0 interrupt
84 * - Enable USART0 clock.
86 #define SER_UART0_IRQ_INIT do { \
87 US0_IDR = 0xFFFFFFFF; \
88 /* Set the vector. */ \
89 AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
90 /* Initialize to edge triggered with defined priority. */ \
91 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
92 /* Enable the USART IRQ */ \
93 AIC_IECR = BV(US0_ID); \
94 PMC_PCER = BV(US0_ID); \
98 #ifndef SER_UART0_BUS_TXINIT
100 * Default TXINIT macro - invoked in uart0_init()
102 * - Disable GPIO on USART0 tx/rx pins
104 * - Set serial param: mode Normal, 8bit data, 1bit stop
105 * - Enable both the receiver and the transmitter
106 * - Enable only the RX complete interrupt
108 #if !CPU_ARM_AT91SAM7S256
109 #warning Check USART0 pins!
111 #define SER_UART0_BUS_TXINIT do { \
112 PIOA_PDR = BV(RXD0) | BV(TXD0); \
113 US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
114 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
115 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
116 US0_IER = BV(US_RXRDY); \
121 #ifndef SER_UART0_BUS_TXBEGIN
123 * Invoked before starting a transmission
125 * - Enable both the receiver and the transmitter
126 * - Enable both the RX complete and TX empty interrupts
128 #define SER_UART0_BUS_TXBEGIN do { \
129 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
130 US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
134 #ifndef SER_UART0_BUS_TXCHAR
136 * Invoked to send one character.
138 #define SER_UART0_BUS_TXCHAR(c) do { \
143 #ifndef SER_UART0_BUS_TXEND
145 * Invoked as soon as the txfifo becomes empty
147 * - Keep both the receiver and the transmitter enabled
148 * - Keep the RX complete interrupt enabled
149 * - Disable the TX empty interrupts
151 #define SER_UART0_BUS_TXEND do { \
152 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
153 US0_IER = BV(US_RXRDY); \
154 US0_IDR = BV(US_TXRDY); \
158 /* End USART0 macros */
160 #ifndef SER_UART1_IRQ_INIT
161 /** \sa SER_UART0_BUS_TXINIT */
162 #define SER_UART1_IRQ_INIT do { \
163 US1_IDR = 0xFFFFFFFF; \
164 /* Set the vector. */ \
165 AIC_SVR(US1_ID) = uart1_irq_dispatcher; \
166 /* Initialize to edge triggered with defined priority. */ \
167 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
168 /* Enable the USART IRQ */ \
169 AIC_IECR = BV(US1_ID); \
170 PMC_PCER = BV(US1_ID); \
174 #ifndef SER_UART1_BUS_TXINIT
175 /** \sa SER_UART1_BUS_TXINIT */
176 #if !CPU_ARM_AT91SAM7S256
177 #warning Check USART1 pins!
179 #define SER_UART1_BUS_TXINIT do { \
180 PIOA_PDR = BV(RXD1) | BV(TXD1); \
181 US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
182 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
183 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
184 US1_IER = BV(US_RXRDY); \
188 #ifndef SER_UART1_BUS_TXBEGIN
189 /** \sa SER_UART1_BUS_TXBEGIN */
190 #define SER_UART1_BUS_TXBEGIN do { \
191 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
192 US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
196 #ifndef SER_UART1_BUS_TXCHAR
197 /** \sa SER_UART1_BUS_TXCHAR */
198 #define SER_UART1_BUS_TXCHAR(c) do { \
203 #ifndef SER_UART1_BUS_TXEND
204 /** \sa SER_UART1_BUS_TXEND */
205 #define SER_UART1_BUS_TXEND do { \
206 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
207 US1_IER = BV(US_RXRDY); \
208 US1_IDR = BV(US_TXRDY); \
212 #ifdef NOT_FOR_ARM_PORT_IT
214 * \name Overridable SPI hooks
216 * These can be redefined in hw.h to implement
217 * special bus policies such as slave select pin handling, etc.
221 #ifndef SER_SPI_BUS_TXINIT
223 * Default TXINIT macro - invoked in spi_init()
224 * The default is no action.
226 #define SER_SPI_BUS_TXINIT
229 #ifndef SER_SPI_BUS_TXCLOSE
231 * Invoked after the last character has been transmitted.
232 * The default is no action.
234 #define SER_SPI_BUS_TXCLOSE
240 * \def CONFIG_SER_STROBE
242 * This is a debug facility that can be used to
243 * monitor SER interrupt activity on an external pin.
245 * To use strobes, redefine the macros SER_STROBE_ON,
246 * SER_STROBE_OFF and SER_STROBE_INIT and set
247 * CONFIG_SER_STROBE to 1.
249 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
250 #define SER_STROBE_ON do {/*nop*/} while(0)
251 #define SER_STROBE_OFF do {/*nop*/} while(0)
252 #define SER_STROBE_INIT do {/*nop*/} while(0)
256 /* From the high-level serial driver */
257 extern struct Serial ser_handles[SER_CNT];
259 /* TX and RX buffers */
260 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
261 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
263 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
264 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
266 #ifdef NOT_FOR_ARM_PORT_IT
267 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
268 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
272 * Internal hardware state structure
274 * The \a sending variable is true while the transmission
275 * interrupt is retriggering itself.
277 * For the USARTs the \a sending flag is useful for taking specific
278 * actions before sending a burst of data, at the start of a trasmission
279 * but not before every char sent.
281 * For the SPI, this flag is necessary because the SPI sends and receives
282 * bytes at the same time and the SPI IRQ is unique for send/receive.
283 * The only way to start transmission is to write data in SPDR (this
284 * is done by spi_starttx()). We do this *only* if a transfer is
285 * not already started.
289 struct SerialHardware hw;
290 volatile bool sending;
295 * These are to trick GCC into *not* using absolute addressing mode
296 * when accessing ser_handles, which is very expensive.
298 * Accessing through these pointers generates much shorter
299 * (and hopefully faster) code.
301 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
302 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
304 #ifdef NOT_FOR_ARM_PORT_IT
305 struct Serial *ser_spi = &ser_handles[SER_SPI];
308 static void uart0_irq_dispatcher(void);
309 static void uart1_irq_dispatcher(void);
311 * Callbacks for USART0
313 static void uart0_init(
314 UNUSED_ARG(struct SerialHardware *, _hw),
315 UNUSED_ARG(struct Serial *, ser))
318 SER_UART0_BUS_TXINIT;
322 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
324 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
327 static void uart0_enabletxirq(struct SerialHardware *_hw)
329 struct ArmSerial *hw = (struct ArmSerial *)_hw;
332 * WARNING: racy code here! The tx interrupt sets hw->sending to false
333 * when it runs with an empty fifo. The order of statements in the
339 SER_UART0_BUS_TXBEGIN;
343 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
345 /* Compute baud-rate period */
346 US0_BRGR = CLOCK_FREQ / (16 * rate);
347 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
350 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
352 US0_MR &= ~US_PAR_MASK;
353 /* Set UART parity */
356 case SER_PARITY_NONE:
362 case SER_PARITY_EVEN:
365 US0_MR |= US_PAR_EVEN;
371 US0_MR |= US_PAR_ODD;
380 * Callbacks for USART1
382 static void uart1_init(
383 UNUSED_ARG(struct SerialHardware *, _hw),
384 UNUSED_ARG(struct Serial *, ser))
387 SER_UART1_BUS_TXINIT;
391 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
393 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
396 static void uart1_enabletxirq(struct SerialHardware *_hw)
398 struct ArmSerial *hw = (struct ArmSerial *)_hw;
401 * WARNING: racy code here! The tx interrupt sets hw->sending to false
402 * when it runs with an empty fifo. The order of statements in the
408 SER_UART1_BUS_TXBEGIN;
412 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
414 /* Compute baud-rate period */
415 US1_BRGR = CLOCK_FREQ / (16 * rate);
416 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
419 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
421 US1_MR &= ~US_PAR_MASK;
422 /* Set UART parity */
425 case SER_PARITY_NONE:
431 case SER_PARITY_EVEN:
434 US1_MR |= US_PAR_EVEN;
440 US1_MR |= US_PAR_ODD;
450 #ifdef NOT_FOR_ARM_PORT_IT
451 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
454 * Set MOSI and SCK ports out, MISO in.
456 * The ATmega64/128 datasheet explicitly states that the input/output
457 * state of the SPI pins is not significant, as when the SPI is
458 * active the I/O port are overrided.
459 * This is *blatantly FALSE*.
461 * Moreover, the MISO pin on the board_kc *must* be in high impedance
462 * state even when the SPI is off, because the line is wired together
463 * with the KBus serial RX, and the transmitter of the slave boards
464 * would be unable to drive the line.
466 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
469 * If the SPI master mode is activated and the SS pin is in input and tied low,
470 * the SPI hardware will automatically switch to slave mode!
471 * For proper communication this pins should therefore be:
473 * - as input but tied high forever!
474 * This driver set the pin as output.
476 #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
477 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
479 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
480 /* Enable SPI, IRQ on, Master */
481 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
484 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
488 /* Set SPI clock rate */
489 #if CONFIG_SPI_CLOCK_DIV == 128
490 SPCR |= (BV(SPR1) | BV(SPR0));
491 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
493 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
495 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
496 // SPR0 & SDPR1 both at 0
498 #error Unsupported SPI clock division factor.
501 /* Set SPI2X bit (spi double frequency) */
502 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
503 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
505 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
508 #error Unsupported SPI clock division factor.
511 /* Set clock polarity */
512 #if CONFIG_SPI_CLOCK_POL == 1
516 /* Set clock phase */
517 #if CONFIG_SPI_CLOCK_PHASE == 1
525 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
531 /* Set all pins as inputs */
532 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
535 static void spi_starttx(struct SerialHardware *_hw)
537 struct AvrSerial *hw = (struct AvrSerial *)_hw;
540 IRQ_SAVE_DISABLE(flags);
542 /* Send data only if the SPI is not already transmitting */
543 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
546 SPDR = fifo_pop(&ser_spi->txfifo);
552 static void spi_setbaudrate(
553 UNUSED_ARG(struct SerialHardware *, _hw),
554 UNUSED_ARG(unsigned long, rate))
559 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
566 static bool tx_sending(struct SerialHardware* _hw)
568 struct ArmSerial *hw = (struct ArmSerial *)_hw;
572 // FIXME: move into compiler.h? Ditch?
574 #define C99INIT(name,val) .name = val
575 #elif defined(__GNUC__)
576 #define C99INIT(name,val) name: val
578 #warning No designated initializers, double check your code
579 #define C99INIT(name,val) (val)
583 * High-level interface data structures
585 static const struct SerialHardwareVT UART0_VT =
587 C99INIT(init, uart0_init),
588 C99INIT(cleanup, uart0_cleanup),
589 C99INIT(setBaudrate, uart0_setbaudrate),
590 C99INIT(setParity, uart0_setparity),
591 C99INIT(txStart, uart0_enabletxirq),
592 C99INIT(txSending, tx_sending),
595 static const struct SerialHardwareVT UART1_VT =
597 C99INIT(init, uart1_init),
598 C99INIT(cleanup, uart1_cleanup),
599 C99INIT(setBaudrate, uart1_setbaudrate),
600 C99INIT(setParity, uart1_setparity),
601 C99INIT(txStart, uart1_enabletxirq),
602 C99INIT(txSending, tx_sending),
605 #ifdef NOT_FOR_ARM_PORT_IT
606 static const struct SerialHardwareVT SPI_VT =
608 C99INIT(init, spi_init),
609 C99INIT(cleanup, spi_cleanup),
610 C99INIT(setBaudrate, spi_setbaudrate),
611 C99INIT(setParity, spi_setparity),
612 C99INIT(txStart, spi_starttx),
613 C99INIT(txSending, tx_sending),
617 static struct ArmSerial UARTDescs[SER_CNT] =
621 C99INIT(table, &UART0_VT),
622 C99INIT(txbuffer, uart0_txbuffer),
623 C99INIT(rxbuffer, uart0_rxbuffer),
624 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
625 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
627 C99INIT(sending, false),
631 C99INIT(table, &UART1_VT),
632 C99INIT(txbuffer, uart1_txbuffer),
633 C99INIT(rxbuffer, uart1_rxbuffer),
634 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
635 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
637 C99INIT(sending, false),
639 #ifdef NOT_FOR_ARM_PORT_IT
642 C99INIT(table, &SPI_VT),
643 C99INIT(txbuffer, spi_txbuffer),
644 C99INIT(rxbuffer, spi_rxbuffer),
645 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
646 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
648 C99INIT(sending, false),
653 struct SerialHardware *ser_hw_getdesc(int unit)
655 ASSERT(unit < SER_CNT);
656 return &UARTDescs[unit].hw;
660 * Serial 0 TX interrupt handler
662 static void uart0_irq_tx(void)
666 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
668 if (fifo_isempty(txfifo))
671 UARTDescs[SER_UART0].sending = false;
675 char c = fifo_pop(txfifo);
676 SER_UART0_BUS_TXCHAR(c);
683 * Serial 0 RX complete interrupt handler.
685 static void uart0_irq_rx(void)
689 /* Should be read before US_CRS */
690 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
693 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
695 if (fifo_isfull(rxfifo))
696 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
698 fifo_push(rxfifo, c);
704 * Serial IRQ dispatcher for USART0.
706 static void uart0_irq_dispatcher(void) __attribute__ ((naked));
707 static void uart0_irq_dispatcher(void)
711 if (US0_IMR & BV(US_RXRDY))
714 if (US0_IMR & BV(US_TXRDY))
721 * Serial 1 TX interrupt handler
723 static void uart1_irq_tx(void)
727 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
729 if (fifo_isempty(txfifo))
732 UARTDescs[SER_UART1].sending = false;
736 char c = fifo_pop(txfifo);
737 SER_UART1_BUS_TXCHAR(c);
744 * Serial 1 RX complete interrupt handler.
746 static void uart1_irq_rx(void)
750 /* Should be read before US_CRS */
751 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
754 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
756 if (fifo_isfull(rxfifo))
757 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
759 fifo_push(rxfifo, c);
765 * Serial IRQ dispatcher for USART1.
767 static void uart1_irq_dispatcher(void) __attribute__ ((naked));
768 static void uart1_irq_dispatcher(void)
772 if (US1_IMR & BV(US_RXRDY))
775 if (US1_IMR & BV(US_TXRDY))