4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
38 * \author Daniele Basile <asterix@develer.com>
43 //#include "ser_at91.h"
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
57 * \name Overridable serial bus hooks
59 * These can be redefined in hw.h to implement
60 * special bus policies such as half-duplex, 485, etc.
64 * TXBEGIN TXCHAR TXEND TXOFF
65 * | __________|__________ | |
68 * ______ __ __ __ __ __ __ ________________
69 * \/ \/ \/ \/ \/ \/ \/
70 * ______/\__/\__/\__/\__/\__/\__/
77 #ifndef SER_UART0_IRQ_INIT
79 * Default IRQ INIT macro - invoked in uart0_init()
81 * - Disable all interrupt
82 * - Register USART0 interrupt
83 * - Enable USART0 clock.
85 #define SER_UART0_IRQ_INIT do { \
86 US0_IDR = 0xFFFFFFFF; \
87 /* Set the vector. */ \
88 AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
89 /* Initialize to edge triggered with defined priority. */ \
90 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \
91 /* Enable the USART IRQ */ \
92 AIC_IECR = BV(US0_ID); \
93 PMC_PCER = BV(US0_ID); \
97 #ifndef SER_UART0_BUS_TXINIT
99 * Default TXINIT macro - invoked in uart0_init()
101 * - Disable GPIO on USART0 tx/rx pins
103 * - Set serial param: mode Normal, 8bit data, 1bit stop
104 * - Enable both the receiver and the transmitter
105 * - Enable only the RX complete interrupt
108 #define SER_UART0_BUS_TXINIT do { \
109 PIOA_PDR = BV(5) | BV(6);\
110 US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
111 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
112 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
113 US0_IER = BV(US_RXRDY); \
115 /*#elif Add other ARM families here */
122 #ifndef SER_UART0_BUS_TXBEGIN
124 * Invoked before starting a transmission
126 * - Enable both the receiver and the transmitter
127 * - Enable both the RX complete and TX empty interrupts
129 #define SER_UART0_BUS_TXBEGIN do { \
130 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
131 US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
135 #ifndef SER_UART0_BUS_TXCHAR
137 * Invoked to send one character.
139 #define SER_UART0_BUS_TXCHAR(c) do { \
144 #ifndef SER_UART0_BUS_TXEND
146 * Invoked as soon as the txfifo becomes empty
148 * - Keep both the receiver and the transmitter enabled
149 * - Keep the RX complete interrupt enabled
150 * - Disable the TX empty interrupts
152 #define SER_UART0_BUS_TXEND do { \
153 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
154 US0_IER = BV(US_RXRDY); \
155 US0_IDR = BV(US_TXRDY); \
159 /* End USART0 macros */
161 #ifndef SER_UART1_IRQ_INIT
162 /** \sa SER_UART0_BUS_TXINIT */
163 #define SER_UART1_IRQ_INIT do { \
164 US1_IDR = 0xFFFFFFFF; \
165 /* Set the vector. */ \
166 AIC_SVR(US1_ID) = uart0_irq_dispatcher; \
167 /* Initialize to edge triggered with defined priority. */ \
168 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; \
169 /* Enable the USART IRQ */ \
170 AIC_IECR = BV(US1_ID); \
171 PMC_PCER = BV(US1_ID); \
175 #ifndef SER_UART1_BUS_TXINIT
176 /** \sa SER_UART1_BUS_TXINIT */
178 #define SER_UART1_BUS_TXINIT do { \
179 PIOA_PDR = BV(0) | BV(1); \
180 US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
181 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
182 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
183 US1_IER = BV(US_RXRDY); \
185 /*#elif Add other ARM families here */
192 #ifndef SER_UART1_BUS_TXBEGIN
193 /** \sa SER_UART1_BUS_TXBEGIN */
194 #define SER_UART1_BUS_TXBEGIN do { \
195 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
196 US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
200 #ifndef SER_UART1_BUS_TXCHAR
201 /** \sa SER_UART1_BUS_TXCHAR */
202 #define SER_UART1_BUS_TXCHAR(c) do { \
207 #ifndef SER_UART1_BUS_TXEND
208 /** \sa SER_UART1_BUS_TXEND */
209 #define SER_UART1_BUS_TXEND do { \
210 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
211 US1_IER = BV(US_RXRDY); \
212 US1_IDR = BV(US_TXRDY); \
217 * \def CONFIG_SER_STROBE
219 * This is a debug facility that can be used to
220 * monitor SER interrupt activity on an external pin.
222 * To use strobes, redefine the macros SER_STROBE_ON,
223 * SER_STROBE_OFF and SER_STROBE_INIT and set
224 * CONFIG_SER_STROBE to 1.
226 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
227 #define SER_STROBE_ON do {/*nop*/} while(0)
228 #define SER_STROBE_OFF do {/*nop*/} while(0)
229 #define SER_STROBE_INIT do {/*nop*/} while(0)
233 /* From the high-level serial driver */
234 extern struct Serial ser_handles[SER_CNT];
236 /* TX and RX buffers */
237 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
238 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
240 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
241 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
244 * Internal hardware state structure
246 * The \a sending variable is true while the transmission
247 * interrupt is retriggering itself.
249 * For the USARTs the \a sending flag is useful for taking specific
250 * actions before sending a burst of data, at the start of a trasmission
251 * but not before every char sent.
253 * For the SPI, this flag is necessary because the SPI sends and receives
254 * bytes at the same time and the SPI IRQ is unique for send/receive.
255 * The only way to start transmission is to write data in SPDR (this
256 * is done by spi_starttx()). We do this *only* if a transfer is
257 * not already started.
261 struct SerialHardware hw;
262 volatile bool sending;
267 * These are to trick GCC into *not* using absolute addressing mode
268 * when accessing ser_handles, which is very expensive.
270 * Accessing through these pointers generates much shorter
271 * (and hopefully faster) code.
273 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
274 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
277 * Serial 0 TX interrupt handler
279 static void usart0_irq_tx(void)
283 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
285 if (fifo_isempty(txfifo))
291 char c = fifo_pop(txfifo);
292 // kprintf("USART0 tx char: %c\n", c);
293 SER_UART0_BUS_TXCHAR(c);
300 * Serial 0 RX complete interrupt handler.
302 static void usart0_irq_rx(void)
306 /* Should be read before US_CRS */
307 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
310 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
312 if (fifo_isfull(rxfifo))
313 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
316 // kprintf("USART0 recv char: %c\n", c);
317 fifo_push(rxfifo, c);
324 * Serial IRQ dispatcher for USART0.
326 static void uart0_irq_dispatcher(void) __attribute__ ((naked));
327 static void uart0_irq_dispatcher(void)
331 if (US0_IMR & BV(US_RXRDY))
333 // kprintf("IRQ RX USART0\n");
336 if (US0_IMR & BV(US_TXRDY))
338 // kprintf("IRQ TX USART0\n");
345 * Serial 1 TX interrupt handler
347 static void usart1_irq_tx(void)
351 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
353 if (fifo_isempty(txfifo))
359 char c = fifo_pop(txfifo);
360 // kprintf("USART1 tx char: %c\n", c);
361 SER_UART1_BUS_TXCHAR(c);
368 * Serial 1 RX complete interrupt handler.
370 static void usart1_irq_rx(void)
374 /* Should be read before US_CRS */
375 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
378 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
380 if (fifo_isfull(rxfifo))
381 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
384 // kprintf("USART1 recv char: %c\n", c);
385 fifo_push(rxfifo, c);
392 * Serial IRQ dispatcher for USART1.
394 static void uart1_irq_dispatcher(void) __attribute__ ((naked));
395 static void uart1_irq_dispatcher(void)
399 if (US1_IMR & BV(US_RXRDY))
401 // kprintf("IRQ RX USART1\n");
404 if (US1_IMR & BV(US_TXRDY))
406 // kprintf("IRQ TX USART1\n");
412 * Callbacks for USART0
414 static void uart0_init(
415 UNUSED_ARG(struct SerialHardware *, _hw),
416 UNUSED_ARG(struct Serial *, ser))
419 SER_UART0_BUS_TXINIT;
423 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
425 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
428 static void uart0_enabletxirq(struct SerialHardware *_hw)
430 struct ArmSerial *hw = (struct ArmSerial *)_hw;
433 * WARNING: racy code here! The tx interrupt sets hw->sending to false
434 * when it runs with an empty fifo. The order of statements in the
440 SER_UART0_BUS_TXBEGIN;
444 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
446 /* Compute baud-rate period */
447 US0_BRGR = CLOCK_FREQ / (16 * rate);
448 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
451 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
453 /* Set UART parity */
456 case SER_PARITY_NONE:
459 US0_MR |= US_PAR_MASK;
462 case SER_PARITY_EVEN:
465 US0_MR |= US_PAR_EVEN;
471 US0_MR |= US_PAR_ODD;
478 * Callbacks for USART1
480 static void uart1_init(
481 UNUSED_ARG(struct SerialHardware *, _hw),
482 UNUSED_ARG(struct Serial *, ser))
485 SER_UART1_BUS_TXINIT;
489 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
491 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
494 static void uart1_enabletxirq(struct SerialHardware *_hw)
496 struct ArmSerial *hw = (struct ArmSerial *)_hw;
499 * WARNING: racy code here! The tx interrupt sets hw->sending to false
500 * when it runs with an empty fifo. The order of statements in the
506 SER_UART1_BUS_TXBEGIN;
510 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
512 /* Compute baud-rate period */
513 US0_BRGR = CLOCK_FREQ / (16 * rate);
514 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
517 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
519 /* Set UART parity */
522 case SER_PARITY_NONE:
525 US1_MR |= US_PAR_MASK;
528 case SER_PARITY_EVEN:
531 US1_MR |= US_PAR_EVEN;
537 US1_MR |= US_PAR_ODD;
544 static bool tx_sending(struct SerialHardware* _hw)
546 struct ArmSerial *hw = (struct ArmSerial *)_hw;
550 // FIXME: move into compiler.h? Ditch?
552 #define C99INIT(name,val) .name = val
553 #elif defined(__GNUC__)
554 #define C99INIT(name,val) name: val
556 #warning No designated initializers, double check your code
557 #define C99INIT(name,val) (val)
561 * High-level interface data structures
563 static const struct SerialHardwareVT UART0_VT =
565 C99INIT(init, uart0_init),
566 C99INIT(cleanup, uart0_cleanup),
567 C99INIT(setBaudrate, uart0_setbaudrate),
568 C99INIT(setParity, uart0_setparity),
569 C99INIT(txStart, uart0_enabletxirq),
570 C99INIT(txSending, tx_sending),
573 static const struct SerialHardwareVT UART1_VT =
575 C99INIT(init, uart0_init),
576 C99INIT(cleanup, uart0_cleanup),
577 C99INIT(setBaudrate, uart0_setbaudrate),
578 C99INIT(setParity, uart0_setparity),
579 C99INIT(txStart, uart0_enabletxirq),
580 C99INIT(txSending, tx_sending),
583 static struct ArmSerial UARTDescs[SER_CNT] =
587 C99INIT(table, &UART0_VT),
588 C99INIT(txbuffer, uart0_txbuffer),
589 C99INIT(rxbuffer, uart0_rxbuffer),
590 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
591 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
593 C99INIT(sending, false),
597 C99INIT(table, &UART1_VT),
598 C99INIT(txbuffer, uart1_txbuffer),
599 C99INIT(rxbuffer, uart1_rxbuffer),
600 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
601 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
603 C99INIT(sending, false),
607 struct SerialHardware *ser_hw_getdesc(int unit)
609 ASSERT(unit < SER_CNT);
610 return &UARTDescs[unit].hw;