4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
38 * \author Daniele Basile <asterix@develer.com>
45 #include <drv/ser_p.h>
47 #include <hw/hw_ser.h> /* Required for bus macros overrides */
48 #include <hw/hw_cpu.h> /* CLOCK_FREQ */
50 #include <mware/fifobuf.h>
51 #include <cfg/debug.h>
53 #include <appconfig.h>
55 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
58 * \name Overridable serial bus hooks
60 * These can be redefined in hw.h to implement
61 * special bus policies such as half-duplex, 485, etc.
65 * TXBEGIN TXCHAR TXEND TXOFF
66 * | __________|__________ | |
69 * ______ __ __ __ __ __ __ ________________
70 * \/ \/ \/ \/ \/ \/ \/
71 * ______/\__/\__/\__/\__/\__/\__/
78 #ifndef SER_UART0_IRQ_INIT
80 * Default IRQ INIT macro - invoked in uart0_init()
82 * - Disable all interrupt
83 * - Register USART0 interrupt
84 * - Enable USART0 clock.
86 #define SER_UART0_IRQ_INIT do { \
87 US0_IDR = 0xFFFFFFFF; \
88 /* Set the vector. */ \
89 AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
90 /* Initialize to edge triggered with defined priority. */ \
91 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
92 /* Enable the USART IRQ */ \
93 AIC_IECR = BV(US0_ID); \
94 PMC_PCER = BV(US0_ID); \
98 #ifndef SER_UART0_BUS_TXINIT
100 * Default TXINIT macro - invoked in uart0_init()
102 * - Disable GPIO on USART0 tx/rx pins
104 * - Set serial param: mode Normal, 8bit data, 1bit stop
105 * - Enable both the receiver and the transmitter
106 * - Enable only the RX complete interrupt
108 #if !CPU_ARM_AT91SAM7S256
109 #warning Check USART0 pins!
111 #define SER_UART0_BUS_TXINIT do { \
112 PIOA_PDR = BV(RXD0) | BV(TXD0); \
113 US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
114 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
115 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
116 US0_IER = BV(US_RXRDY); \
121 #ifndef SER_UART0_BUS_TXBEGIN
123 * Invoked before starting a transmission
125 * - Enable both the receiver and the transmitter
126 * - Enable both the RX complete and TX empty interrupts
128 #define SER_UART0_BUS_TXBEGIN do { \
129 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
130 US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
134 #ifndef SER_UART0_BUS_TXCHAR
136 * Invoked to send one character.
138 #define SER_UART0_BUS_TXCHAR(c) do { \
143 #ifndef SER_UART0_BUS_TXEND
145 * Invoked as soon as the txfifo becomes empty
147 * - Keep both the receiver and the transmitter enabled
148 * - Keep the RX complete interrupt enabled
149 * - Disable the TX empty interrupts
151 #define SER_UART0_BUS_TXEND do { \
152 US0_CR = BV(US_RXEN) | BV(US_TXEN); \
153 US0_IER = BV(US_RXRDY); \
154 US0_IDR = BV(US_TXRDY); \
158 /* End USART0 macros */
160 #ifndef SER_UART1_IRQ_INIT
161 /** \sa SER_UART0_BUS_TXINIT */
162 #define SER_UART1_IRQ_INIT do { \
163 US1_IDR = 0xFFFFFFFF; \
164 /* Set the vector. */ \
165 AIC_SVR(US1_ID) = uart1_irq_dispatcher; \
166 /* Initialize to edge triggered with defined priority. */ \
167 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
168 /* Enable the USART IRQ */ \
169 AIC_IECR = BV(US1_ID); \
170 PMC_PCER = BV(US1_ID); \
174 #ifndef SER_UART1_BUS_TXINIT
175 /** \sa SER_UART1_BUS_TXINIT */
176 #if !CPU_ARM_AT91SAM7S256
177 #warning Check USART1 pins!
179 #define SER_UART1_BUS_TXINIT do { \
180 PIOA_PDR = BV(RXD1) | BV(TXD1); \
181 US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
182 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
183 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
184 US1_IER = BV(US_RXRDY); \
188 #ifndef SER_UART1_BUS_TXBEGIN
189 /** \sa SER_UART1_BUS_TXBEGIN */
190 #define SER_UART1_BUS_TXBEGIN do { \
191 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
192 US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
196 #ifndef SER_UART1_BUS_TXCHAR
197 /** \sa SER_UART1_BUS_TXCHAR */
198 #define SER_UART1_BUS_TXCHAR(c) do { \
203 #ifndef SER_UART1_BUS_TXEND
204 /** \sa SER_UART1_BUS_TXEND */
205 #define SER_UART1_BUS_TXEND do { \
206 US1_CR = BV(US_RXEN) | BV(US_TXEN); \
207 US1_IER = BV(US_RXRDY); \
208 US1_IDR = BV(US_TXRDY); \
213 * \name Overridable SPI hooks
215 * These can be redefined in hw.h to implement
216 * special bus policies such as slave select pin handling, etc.
220 #ifndef SER_SPI_BUS_TXINIT
222 * Default TXINIT macro - invoked in spi_init()
223 * The default is no action.
225 #define SER_SPI_BUS_TXINIT
228 #ifndef SER_SPI_BUS_TXCLOSE
230 * Invoked after the last character has been transmitted.
231 * The default is no action.
233 #define SER_SPI_BUS_TXCLOSE
239 * \def CONFIG_SER_STROBE
241 * This is a debug facility that can be used to
242 * monitor SER interrupt activity on an external pin.
244 * To use strobes, redefine the macros SER_STROBE_ON,
245 * SER_STROBE_OFF and SER_STROBE_INIT and set
246 * CONFIG_SER_STROBE to 1.
248 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
249 #define SER_STROBE_ON do {/*nop*/} while(0)
250 #define SER_STROBE_OFF do {/*nop*/} while(0)
251 #define SER_STROBE_INIT do {/*nop*/} while(0)
255 /* From the high-level serial driver */
256 extern struct Serial ser_handles[SER_CNT];
258 /* TX and RX buffers */
259 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
260 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
262 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
263 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
265 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
266 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
269 * Internal hardware state structure
271 * The \a sending variable is true while the transmission
272 * interrupt is retriggering itself.
274 * For the USARTs the \a sending flag is useful for taking specific
275 * actions before sending a burst of data, at the start of a trasmission
276 * but not before every char sent.
278 * For the SPI, this flag is necessary because the SPI sends and receives
279 * bytes at the same time and the SPI IRQ is unique for send/receive.
280 * The only way to start transmission is to write data in SPDR (this
281 * is done by spi_starttx()). We do this *only* if a transfer is
282 * not already started.
286 struct SerialHardware hw;
287 volatile bool sending;
292 * These are to trick GCC into *not* using absolute addressing mode
293 * when accessing ser_handles, which is very expensive.
295 * Accessing through these pointers generates much shorter
296 * (and hopefully faster) code.
298 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
299 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
300 struct Serial *ser_spi = &ser_handles[SER_SPI];
302 static void uart0_irq_dispatcher(void);
303 static void uart1_irq_dispatcher(void);
305 * Callbacks for USART0
307 static void uart0_init(
308 UNUSED_ARG(struct SerialHardware *, _hw),
309 UNUSED_ARG(struct Serial *, ser))
312 SER_UART0_BUS_TXINIT;
316 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
318 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
321 static void uart0_enabletxirq(struct SerialHardware *_hw)
323 struct ArmSerial *hw = (struct ArmSerial *)_hw;
326 * WARNING: racy code here! The tx interrupt sets hw->sending to false
327 * when it runs with an empty fifo. The order of statements in the
333 SER_UART0_BUS_TXBEGIN;
337 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
339 /* Compute baud-rate period */
340 US0_BRGR = CLOCK_FREQ / (16 * rate);
341 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
344 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
346 US0_MR &= ~US_PAR_MASK;
347 /* Set UART parity */
350 case SER_PARITY_NONE:
356 case SER_PARITY_EVEN:
359 US0_MR |= US_PAR_EVEN;
365 US0_MR |= US_PAR_ODD;
374 * Callbacks for USART1
376 static void uart1_init(
377 UNUSED_ARG(struct SerialHardware *, _hw),
378 UNUSED_ARG(struct Serial *, ser))
381 SER_UART1_BUS_TXINIT;
385 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
387 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
390 static void uart1_enabletxirq(struct SerialHardware *_hw)
392 struct ArmSerial *hw = (struct ArmSerial *)_hw;
395 * WARNING: racy code here! The tx interrupt sets hw->sending to false
396 * when it runs with an empty fifo. The order of statements in the
402 SER_UART1_BUS_TXBEGIN;
406 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
408 /* Compute baud-rate period */
409 US1_BRGR = CLOCK_FREQ / (16 * rate);
410 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
413 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
415 US1_MR &= ~US_PAR_MASK;
416 /* Set UART parity */
419 case SER_PARITY_NONE:
425 case SER_PARITY_EVEN:
428 US1_MR |= US_PAR_EVEN;
434 US1_MR |= US_PAR_ODD;
445 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
448 * Set MOSI and SCK ports out, MISO in.
450 * The ATmega64/128 datasheet explicitly states that the input/output
451 * state of the SPI pins is not significant, as when the SPI is
452 * active the I/O port are overrided.
453 * This is *blatantly FALSE*.
455 * Moreover, the MISO pin on the board_kc *must* be in high impedance
456 * state even when the SPI is off, because the line is wired together
457 * with the KBus serial RX, and the transmitter of the slave boards
458 * would be unable to drive the line.
460 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
463 * If the SPI master mode is activated and the SS pin is in input and tied low,
464 * the SPI hardware will automatically switch to slave mode!
465 * For proper communication this pins should therefore be:
467 * - as input but tied high forever!
468 * This driver set the pin as output.
470 #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
471 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
473 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
474 /* Enable SPI, IRQ on, Master */
475 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
478 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
482 /* Set SPI clock rate */
483 #if CONFIG_SPI_CLOCK_DIV == 128
484 SPCR |= (BV(SPR1) | BV(SPR0));
485 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
487 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
489 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
490 // SPR0 & SDPR1 both at 0
492 #error Unsupported SPI clock division factor.
495 /* Set SPI2X bit (spi double frequency) */
496 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
497 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
499 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
502 #error Unsupported SPI clock division factor.
505 /* Set clock polarity */
506 #if CONFIG_SPI_CLOCK_POL == 1
510 /* Set clock phase */
511 #if CONFIG_SPI_CLOCK_PHASE == 1
519 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
525 /* Set all pins as inputs */
526 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
529 static void spi_starttx(struct SerialHardware *_hw)
531 struct AvrSerial *hw = (struct AvrSerial *)_hw;
534 IRQ_SAVE_DISABLE(flags);
536 /* Send data only if the SPI is not already transmitting */
537 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
540 SPDR = fifo_pop(&ser_spi->txfifo);
546 static void spi_setbaudrate(
547 UNUSED_ARG(struct SerialHardware *, _hw),
548 UNUSED_ARG(unsigned long, rate))
553 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
560 static bool tx_sending(struct SerialHardware* _hw)
562 struct ArmSerial *hw = (struct ArmSerial *)_hw;
566 // FIXME: move into compiler.h? Ditch?
568 #define C99INIT(name,val) .name = val
569 #elif defined(__GNUC__)
570 #define C99INIT(name,val) name: val
572 #warning No designated initializers, double check your code
573 #define C99INIT(name,val) (val)
577 * High-level interface data structures
579 static const struct SerialHardwareVT UART0_VT =
581 C99INIT(init, uart0_init),
582 C99INIT(cleanup, uart0_cleanup),
583 C99INIT(setBaudrate, uart0_setbaudrate),
584 C99INIT(setParity, uart0_setparity),
585 C99INIT(txStart, uart0_enabletxirq),
586 C99INIT(txSending, tx_sending),
589 static const struct SerialHardwareVT UART1_VT =
591 C99INIT(init, uart1_init),
592 C99INIT(cleanup, uart1_cleanup),
593 C99INIT(setBaudrate, uart1_setbaudrate),
594 C99INIT(setParity, uart1_setparity),
595 C99INIT(txStart, uart1_enabletxirq),
596 C99INIT(txSending, tx_sending),
599 static const struct SerialHardwareVT SPI_VT =
601 C99INIT(init, spi_init),
602 C99INIT(cleanup, spi_cleanup),
603 C99INIT(setBaudrate, spi_setbaudrate),
604 C99INIT(setParity, spi_setparity),
605 C99INIT(txStart, spi_starttx),
606 C99INIT(txSending, tx_sending),
609 static struct ArmSerial UARTDescs[SER_CNT] =
613 C99INIT(table, &UART0_VT),
614 C99INIT(txbuffer, uart0_txbuffer),
615 C99INIT(rxbuffer, uart0_rxbuffer),
616 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
617 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
619 C99INIT(sending, false),
623 C99INIT(table, &UART1_VT),
624 C99INIT(txbuffer, uart1_txbuffer),
625 C99INIT(rxbuffer, uart1_rxbuffer),
626 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
627 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
629 C99INIT(sending, false),
633 C99INIT(table, &SPI_VT),
634 C99INIT(txbuffer, spi_txbuffer),
635 C99INIT(rxbuffer, spi_rxbuffer),
636 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
637 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
639 C99INIT(sending, false),
643 struct SerialHardware *ser_hw_getdesc(int unit)
645 ASSERT(unit < SER_CNT);
646 return &UARTDescs[unit].hw;
650 * Serial 0 TX interrupt handler
652 static void uart0_irq_tx(void)
656 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
658 if (fifo_isempty(txfifo))
661 UARTDescs[SER_UART0].sending = false;
665 char c = fifo_pop(txfifo);
666 SER_UART0_BUS_TXCHAR(c);
673 * Serial 0 RX complete interrupt handler.
675 static void uart0_irq_rx(void)
679 /* Should be read before US_CRS */
680 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
683 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
685 if (fifo_isfull(rxfifo))
686 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
688 fifo_push(rxfifo, c);
694 * Serial IRQ dispatcher for USART0.
696 static void uart0_irq_dispatcher(void) __attribute__ ((naked));
697 static void uart0_irq_dispatcher(void)
701 if (US0_IMR & BV(US_RXRDY))
704 if (US0_IMR & BV(US_TXRDY))
711 * Serial 1 TX interrupt handler
713 static void uart1_irq_tx(void)
717 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
719 if (fifo_isempty(txfifo))
722 UARTDescs[SER_UART1].sending = false;
726 char c = fifo_pop(txfifo);
727 SER_UART1_BUS_TXCHAR(c);
734 * Serial 1 RX complete interrupt handler.
736 static void uart1_irq_rx(void)
740 /* Should be read before US_CRS */
741 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
744 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
746 if (fifo_isfull(rxfifo))
747 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
749 fifo_push(rxfifo, c);
755 * Serial IRQ dispatcher for USART1.
757 static void uart1_irq_dispatcher(void) __attribute__ ((naked));
758 static void uart1_irq_dispatcher(void)
762 if (US1_IMR & BV(US_RXRDY))
765 if (US1_IMR & BV(US_TXRDY))