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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief SPI driver with DMA.
35 * \author Francesco Sacchi <batt@develer.com>
36 * \author Luca Ottaviano <lottaviano@develer.com>
39 #include "cfg/cfg_spi_dma.h"
41 #include "spi_dma_at91.h"
42 #include "hw/hw_spi_dma.h"
45 #include <struct/fifobuf.h>
46 #include <struct/kfile_fifo.h>
47 #include <drv/timer.h>
50 #include <cpu/power.h>
52 #include <string.h> /* memset */
54 static uint8_t tx_fifo_buffer[CONFIG_SPI_DMA_TXBUFSIZE];
55 static FIFOBuffer tx_fifo;
56 static KFileFifo kfifo;
59 INLINE void spi_dma_startTx(void)
61 if (fifo_isempty(&tx_fifo))
64 if (SPI0_SR & BV(SPI_TXBUFE))
66 SPI0_PTCR = BV(PDC_TXTDIS);
67 SPI0_TPR = (reg32_t)tx_fifo.head;
68 if (tx_fifo.head < tx_fifo.tail)
69 SPI0_TCR = tx_fifo.tail - tx_fifo.head;
71 SPI0_TCR = tx_fifo.end - tx_fifo.head + 1;
73 SPI0_PTCR = BV(PDC_TXTEN);
77 static DECLARE_ISR(spi0_dma_write_irq_handler)
80 /* Pop sent chars from FIFO */
81 tx_fifo.head = (uint8_t *)SPI0_TPR;
82 if (tx_fifo.head > tx_fifo.end)
83 tx_fifo.head = tx_fifo.begin;
92 void spi_dma_setclock(uint32_t rate)
94 SPI0_CSR0 &= ~SPI_SCBR;
96 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
97 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
100 static size_t spi_dma_write(UNUSED_ARG(struct KFile *, fd), const void *_buf, size_t size)
102 size_t count, total_wr = 0;
103 const uint8_t *buf = (const uint8_t *) _buf;
105 // copy buffer to internal fifo
108 #if CONFIG_SPI_DMA_TX_TIMEOUT != -1
109 ticks_t start = timer_clock();
110 while (fifo_isfull(&tx_fifo) && (timer_clock() - start < ms_to_ticks(CONFIG_SPI_DMA_TX_TIMEOUT)))
113 if (fifo_isfull(&tx_fifo))
116 while (fifo_isfull(&tx_fifo))
118 #endif /* CONFIG_SPI_DMA_TX_TIMEOUT */
120 // FIXME: improve copy performance
121 count = kfile_write(&kfifo.fd, buf, size);
131 static int spi_dma_flush(UNUSED_ARG(struct KFile *, fd))
133 /* Wait FIFO flush */
134 while (!fifo_isempty(&tx_fifo))
137 /* Wait until last bit has been shifted out */
138 while (!(SPI0_SR & BV(SPI_TXEMPTY)))
144 static DECLARE_ISR(spi0_dma_read_irq_handler)
151 * Dummy buffer used to transmit 0xff chars while receiving data.
152 * This buffer is completetly constant and the compiler should allocate it
155 static const uint8_t tx_dummy_buf[CONFIG_SPI_DMA_MAX_RX] = { [0 ... (CONFIG_SPI_DMA_MAX_RX - 1)] = 0xFF };
157 static size_t spi_dma_read(struct KFile *fd, void *_buf, size_t size)
159 size_t count, total_rx = 0;
160 uint8_t *buf = (uint8_t *)_buf;
164 /* Dummy irq handler that do nothing */
165 AIC_SVR(SPI0_ID) = spi0_dma_read_irq_handler;
169 count = MIN(size, (size_t)CONFIG_SPI_DMA_MAX_RX);
171 SPI0_PTCR = BV(PDC_TXTDIS) | BV(PDC_RXTDIS);
173 SPI0_RPR = (reg32_t)buf;
175 SPI0_TPR = (reg32_t)tx_dummy_buf;
178 /* Avoid reading the previous sent char */
182 SPI0_PTCR = BV(PDC_RXTEN) | BV(PDC_TXTEN);
184 /* wait for transfer to finish */
185 while (!(SPI0_SR & BV(SPI_ENDRX)))
192 SPI0_PTCR = BV(PDC_RXTDIS) | BV(PDC_TXTDIS);
194 /* set write irq handler back in place */
195 AIC_SVR(SPI0_ID) = spi0_dma_write_irq_handler;
200 #define SPI_DMA_IRQ_PRIORITY 4
202 void spi_dma_init(SpiDmaAt91 *spi)
204 /* Disable PIO on SPI pins */
205 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
208 SPI0_CR = BV(SPI_SWRST);
211 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
212 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
214 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
218 * At reset clock division factor is set to 0, that is
219 * *forbidden*. Set SPI clock to minimum to keep it valid.
221 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
223 /* Disable all irqs */
224 SPI0_IDR = 0xFFFFFFFF;
225 /* Set the vector. */
226 AIC_SVR(SPI0_ID) = spi0_dma_write_irq_handler;
227 /* Initialize to edge triggered with defined priority. */
228 AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SPI_DMA_IRQ_PRIORITY;
229 /* Enable the USART IRQ */
230 AIC_IECR = BV(SPI0_ID);
231 PMC_PCER = BV(SPI0_ID);
233 /* Enable interrupt on tx buffer empty */
234 SPI0_IER = BV(SPI_ENDTX);
237 SPI0_CR = BV(SPI_SPIEN);
239 DB(spi->fd._type = KFT_SPIDMAAT91);
240 spi->fd.write = spi_dma_write;
241 spi->fd.read = spi_dma_read;
242 spi->fd.flush = spi_dma_flush;
244 fifo_init(&tx_fifo, tx_fifo_buffer, sizeof(tx_fifo_buffer));
245 kfilefifo_init(&kfifo, &tx_fifo);
247 SPI_DMA_STROBE_INIT();