4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
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11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91 reset controller.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
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55 * from this software without specific prior written permission.
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70 * For additional information see http://www.ethernut.de/
76 /** Reset Controller Control Register */
78 #define RSTC_CR (*((volatile uint32_t *)(RSTC_BASE + 0x00))) ///< Reset controller control register address.
79 #define RSTC_PROCRST 0 ///< Processor reset.
80 #define RSTC_PERRST 2 ///< Peripheral reset.
81 #define RSTC_EXTRST 3 ///< External reset.
82 #define RSTC_KEY 0xA5000000 ///< Password.
85 /** Reset Controller Status Register */
87 #define RSTC_SR (*((volatile uint32_t *)(RSTC_BASE + 0x04))) ///< Reset controller status register address.
88 #define RSTC_URSTS 0 ///< User reset status.
89 #define RSTC_BODSTS 1 ///< Brownout detection status.
90 #define RSTC_RSTTYP_MASK 0x00000700 ///< Reset type.
91 #define RSTC_RSTTYP_POWERUP 0x00000000 ///< Power-up reset.
92 //#define RSTC_RSTTYP_WAKEUP 0x00000100 ///< VDDCORE rising.
93 #define RSTC_RSTTYP_WATCHDOG 0x00000200 ///< Watchdog reset.
94 #define RSTC_RSTTYP_SOFTWARE 0x00000300 ///< Software reset.
95 #define RSTC_RSTTYP_USER 0x00000400 ///< User reset.
96 #define RSTC_RSTTYP_BROWNOUT 0x00000500 ///< Brownout reset.
97 #define RSTC_NRSTL 16 ///< NRST pin level.
98 #define RSTC_SRCMP 17 ///< Software reset command in progress.
101 /** Reset Controller Mode Register */
103 #define RSTC_MR (*((volatile uint32_t *)(RSTC_BASE + 0x08))) ///< Reset controller mode register address.
104 #define RSTC_URSTEN 0 ///< User reset enable.
105 #define RSTC_URSTIEN 4 ///< User reset interrupt enable.
106 #define RSTC_ERSTL_MASK 0x00000F00 ///< External reset length.
107 #define RSTC_ERSTL_SHIFT 8 ///< Least significant bit of external reset length.
108 #define RSTC_BODIEN 16 ///< Brown-out detection interrupt enable.
112 #endif /* AT91_RTSC_H */