4 * This file is part of BeRTOS.
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27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
33 * \version $Id: at91_aic.h 18260 2007-10-11 14:08:10Z batt $
35 * \author Daniele Basile <asterix@develer.com>
37 * AT91 UART User interface.
38 * This file is based on NUT/OS implementation. See license below.
41 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of the copyright holders nor the names of
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
60 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
62 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
63 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
64 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
66 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * For additional information see http://www.ethernut.de/
76 * USART Control Register
79 #define US_CR_OFF 0x00000000 ///< USART control register offset.
80 #define US0_CR (*((reg32_t *)(USART0_BASE + US_CR_OFF))) ///< Channel 0 control register address.
81 #define US1_CR (*((reg32_t *)(USART1_BASE + US_CR_OFF))) ///< Channel 1 control register address.
82 #define US_RSTRX 2 ///< Reset receiver.
83 #define US_RSTTX 3 ///< Reset transmitter.
84 #define US_RXEN 4 ///< Receiver enable.
85 #define US_RXDIS 5 ///< Receiver disable.
86 #define US_TXEN 6 ///< Transmitter enable.
87 #define US_TXDIS 7 ///< Transmitter disable.
88 #define US_RSTSTA 8 ///< Reset status bits.
89 #define US_STTBRK 9 ///< Start break.
90 #define US_STPBRK 10 ///< Stop break.
91 #define US_STTTO 11 ///< Start timeout.
92 #define US_SENDA 12 ///< Send next byte with address bit set.
93 #define US_RSTIT 13 ///< Reset interations.
94 #define US_RSTNAK 14 ///< Reset non acknowledge.
95 #define US_RETTO 15 ///< Rearm time out.
96 #define US_DTREN 16 ///< Data terminal ready enable.
97 #define US_DTRDIS 17 ///< Data terminal ready disable.
98 #define US_RTSEN 18 ///< Request to send enable.
99 #define US_RTSDIS 19 ///< Request to send disable.
106 #define US_MR_OFF 0x00000004 ///< USART mode register offset.
107 #define US0_MR (*((reg32_t *)(USART0_BASE + US_MR_OFF))) ///< Channel 0 mode register address.
108 #define US1_MR (*((reg32_t *)(USART1_BASE + US_MR_OFF))) ///< Channel 1 mode register address.
110 #define US_USART_MODE_MASK 0x0000000F ///< USART mode mask.
111 #define US_USART_MODE_NORMA 0x00000000 ///< Normal.
112 #define US_USART_MODE_RS485 0x00000001 ///< RS485.
113 #define US_USART_MODE_HW_HDSH 0x00000002 ///< Hardware handshaking.
114 #define US_USART_MODE_MODEM 0x00000003 ///< Modem.
115 #define US_USART_MODE_ISO7816T0 0x00000004 ///< ISO7816 protocol: T=0.
116 #define US_USART_MODE_ISO7816T1 0x00000006 ///< ISO7816 protocol: T=1.
117 #define US_USART_MODE_IRDA 0x00000008 ///< IrDA.
119 #define US_CLKS_MASK 0x00000030 ///< Clock selection mask.
120 #define US_CLKS_MCK 0x00000000 ///< Master clock.
121 #define US_CLKS_MCK8 0x00000010 ///< Master clock divided by 8.
122 #define US_CLKS_SCK 0x00000020 ///< External clock.
123 #define US_CLKS_SLCK 0x00000030 ///< Slow clock.
125 #define US_CHRL_MASK 0x000000C0 ///< Masks data length.
126 #define US_CHRL_5 0x00000000 ///< 5 data bits.
127 #define US_CHRL_6 0x00000040 ///< 6 data bits.
128 #define US_CHRL_7 0x00000080 ///< 7 data bits.
129 #define US_CHRL_8 0x000000C0 ///< 8 data bits.
131 #define US_SYNC 8 ///< Synchronous mode enable.
133 #define US_PAR_MASK 0x00000E00 ///< Parity mode mask.
134 #define US_PAR_EVEN 0x00000000 ///< Even parity.
135 #define US_PAR_ODD 0x00000200 ///< Odd parity.
136 #define US_PAR_SPACE 0x00000400 ///< Space parity.
137 #define US_PAR_MARK 0x00000600 ///< Marked parity.
138 #define US_PAR_NO 0x00000800 ///< No parity.
139 #define US_PAR_MULTIDROP 0x00000C00 ///< Multi-drop mode.
141 #define US_NBSTOP_MASK 0x00003000 ///< Masks stop bit length.
142 #define US_NBSTOP_1 0x00000000 ///< 1 stop bit.
143 #define US_NBSTOP_1_5 0x00001000 ///< 1.5 stop bits.
144 #define US_NBSTOP_2 0x00002000 ///< 2 stop bits.
146 #define US_CHMODE_MASK 0x0000C000 ///< Channel mode mask.
147 #define US_CHMODE_NORMAL 0x00000000 ///< Normal mode.
148 #define US_CHMODE_AUTOMATIC_ECHO 0x00004000 ///< Automatic echo.
149 #define US_CHMODE_LOCAL_LOOPBACK 0x00008000 ///< Local loopback.
150 #define US_CHMODE_REMOTE_LOOPBACK 0x0000C000 ///< Remote loopback.
152 #define US_MSBF 16 ///< Bit order.
153 #define US_MODE9 17 ///< 9 bit mode.
154 #define US_CLKO 18 ///< Clock output select.
155 #define US_OVER 19 ///< Oversampling mode.
156 #define US_INACK 20 ///< Inhibit non acknowledge.
157 #define US_DSNACK 21 ///< Disable successive nack.
159 #define US_MAX_INTERATION_MASK 0x07000000 ///< Max numer of interation in mode ISO7816 T=0.
161 #define US_FILTER 28 ///< Infrared receive line filter.
166 * Status and Interrupt Register
169 #define US_IER_OFF 0x00000008 ///< USART interrupt enable register offset.
170 #define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF))) ///< Channel 0 interrupt enable register address.
171 #define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF))) ///< Channel 1 interrupt enable register address.
173 #define US_IDR_OFF 0x0000000C ///< USART interrupt disable register offset.
174 #define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF))) ///< Channel 0 interrupt disable register address.
175 #define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF))) ///< Channel 1 interrupt disable register address.
177 #define US_IMR_OFF 0x00000010 ///< USART interrupt mask register offset.
178 #define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF))) ///< Channel 0 interrupt mask register address.
179 #define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF))) ///< Channel 1 interrupt mask register address.
181 #define US_CSR_OFF 0x00000014 ///< USART status register offset.
182 #define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF))) ///< Channel 0 status register address.
183 #define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF))) ///< Channel 1 status register address.
184 #define US_CSR_RI 20 ///< Image of RI input.
185 #define US_CSR_DSR 21 ///< Image of DSR input.
186 #define US_CSR_DCD 22 ///< Image of DCD input.
187 #define US_CSR_CTS 23 ///< Image of CTS input.
189 #define US_RXRDY 0 ///< Receiver ready.
190 #define US_TXRDY 1 ///< Transmitter ready.
191 #define US_RXBRK 2 ///< Receiver break.
192 #define US_ENDRX 3 ///< End of receiver PDC transfer.
193 #define US_ENDTX 4 ///< End of transmitter PDC transfer.
194 #define US_OVRE 5 ///< Overrun error.
195 #define US_FRAME 6 ///< Framing error.
196 #define US_PARE 7 ///< Parity error.
197 #define US_TIMEOUT 8 ///< Receiver timeout.
198 #define US_TXEMPTY 9 ///< Transmitter empty.
199 #define US_ITERATION 10 ///< Iteration interrupt enable.
200 #define US_TXBUFE 11 ///< Buffer empty interrupt enable.
201 #define US_RXBUFF 12 ///< Buffer full interrupt enable.
202 #define US_NACK 13 ///< Non acknowledge interrupt enable.
203 #define US_RIIC 16 ///< Ring indicator input change enable.
204 #define US_DSRIC 17 ///< Data set ready input change enable.
205 #define US_DCDIC 18 ///< Data carrier detect input change interrupt enable.
206 #define US_CTSIC 19 ///< Clear to send input change interrupt enable.
209 * Receiver Holding Register
212 #define US_RHR_OFF 0x00000018 ///< USART receiver holding register offset.
213 #define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF))) ///< Channel 0 receiver holding register address.
214 #define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF))) ///< Channel 1 receiver holding register address.
215 #define US_RHR_RXCHR_MASK 0x000001FF ///< Last char received if US_RXRDY is set.
216 #define US_RHR_RXSYNH 15 ///< Received sync.
220 * Transmitter Holding Register
223 #define US_THR_OFF 0x0000001C ///< USART transmitter holding register offset.
224 #define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF))) ///< Channel 0 transmitter holding register address.
225 #define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF))) ///< Channel 1 transmitter holding register address.
226 #define US_THR_TXCHR_MASK 0x000001FF ///< Next char to be trasmitted.
227 #define US_THR_TXSYNH 15 ///< Sync field to be trasmitted.
231 * Baud Rate Generator Register
234 #define US_BRGR_OFF 0x00000020 ///< USART baud rate register offset.
235 #define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF))) ///< Channel 0 baud rate register address.
236 #define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF))) ///< Channel 1 baud rate register address.
240 * Receiver Timeout Register
243 #define US_RTOR_OFF 0x00000024 ///< USART receiver timeout register offset.
244 #define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF))) ///< Channel 0 receiver timeout register address.
245 #define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF))) ///< Channel 1 receiver timeout register address.
249 * Transmitter Time Guard Register
252 #define US_TTGR_OFF 0x00000028 ///< USART transmitter time guard register offset.
253 #define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF))) ///< Channel 0 transmitter time guard register address.
254 #define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF))) ///< Channel 1 transmitter time guard register address.
258 * FI DI Ratio Register
261 #define US_FIDI_OFF 0x00000040 ///< USART FI DI ratio register offset.
262 #define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF))) ///< Channel 0 FI DI ratio register address.
263 #define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF))) ///< Channel 1 FI DI ratio register address.
267 * Error Counter Register
270 #define US_NER_OFF 0x00000044 ///< USART error counter register offset.
271 #define US0_NER (*((reg32_t *)(USART0_BASE + US_NER_OFF))) ///< Channel 0 error counter register address.
272 #define US1_NER (*((reg32_t *)(USART1_BASE + US_NER_OFF))) ///< Channel 1 error counter register address.
276 * IrDA Filter Register
279 #define US_IF_OFF 0x0000004C ///< USART IrDA filter register offset.
280 #define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF))) ///< Channel 0 IrDA filter register address.
281 #define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF))) ///< Channel 1 IrDA filter register address.
287 * Receive Pointer Register
290 #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF))) ///< Channel 0 receive pointer register address.
291 #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF))) ///< Channel 1 receive pointer register address.
295 * Receive Counter Register
298 #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF))) ///< Channel 0 receive counter register address.
299 #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF))) ///< Channel 1 receive counter register address.
303 * Transmit Pointer Register
306 #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF))) ///< Channel 0 transmit pointer register address.
307 #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF))) ///< Channel 1 transmit pointer register address.
311 * Transmit Counter Register
314 #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF))) ///< Channel 0 transmit counter register address.
315 #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF))) ///< Channel 1 transmit counter register address.
318 #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
319 #define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
320 #define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
321 #define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
322 #define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
325 #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
326 #define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
327 #define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
328 #define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
329 #define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
332 #if defined(PERIPH_PTCR_OFF)
333 #define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
334 #define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
337 #if defined(PERIPH_PTSR_OFF)
338 #define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
339 #define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
342 #endif /* USART_HAS_PDC */
346 * SPI Control Register
349 #define SPI_CR_OFF 0x00000000 ///< Control register offset.
350 #define SPI_CR (*((reg32_t *)(SPI_BASE + SPI_CR_OFF))) ///< SPI control register.
351 #define SPI_SPIEN 0 ///< SPI enable.
352 #define SPI_SPIDIS 1 ///< SPI disable.
353 #define SPI_SWRST 7 ///< Software reset.
354 #define SPI_LASTXFER 24 ///< Last transfer.
361 #define SPI_MR_OFF 0x00000004 ///< Mode register offset.
362 #define SPI_MR (*((reg32_t *)(SPI_BASE + SPI_MR_OFF))) ///< SPI mode register.
363 #define SPI_MSTR 0 ///< Master mode.
364 #define SPI_PS 1 ///< Peripheral select.
365 #define SPI_PCSDEC 2 ///< Chip select decode.
366 #define SPI_MODFDIS 4 ///< Mode fault detection.
367 #define SPI_LLB 7 ///< Local loopback enable.
368 #define SPI_PCS 0x000F0000 ///< Peripheral chip select mask.
369 #define SPI_PCS_0 0x000E0000 ///< Peripheral chip select 0.
370 #define SPI_PCS_1 0x000D0000 ///< Peripheral chip select 1.
371 #define SPI_PCS_2 0x000B0000 ///< Peripheral chip select 2.
372 #define SPI_PCS_3 0x00070000 ///< Peripheral chip select 3.
373 #define SPI_PCS_LSB 16 ///< Least significant bit of peripheral chip select.
374 #define SPI_DLYBCS 0xFF000000 ///< Mask for delay between chip selects.
375 #define SPI_DLYBCS_LSB 24 ///< Least significant bit of delay between chip selects.
379 * SPI Receive Data Register
382 #define SPI_RDR_OFF 0x00000008 ///< Receive data register offset.
383 #define SPI_RDR (*((reg32_t *)(SPI_BASE + SPI_RDR_OFF))) ///< SPI receive data register.
384 #define SPI_RD 0x0000FFFF ///< Receive data mask.
385 #define SPI_RD_LSB 0 ///< Least significant bit of receive data.
389 * SPI Transmit Data Register
392 #define SPI_TDR_OFF 0x0000000C ///< Transmit data register offset.
393 #define SPI_TDR (*((reg32_t *)(SPI_BASE + SPI_TDR_OFF))) ///< SPI transmit data register.
394 #define SPI_TD 0x0000FFFF ///< Transmit data mask.
395 #define SPI_TD_LSB 0 ///< Least significant bit of transmit data.
399 * SPI Status and Interrupt Register
402 #define SPI_SR_OFF 0x00000010 ///< Status register offset.
403 #define SPI_SR (*((reg32_t *)(SPI_BASE + SPI_SR_OFF))) ///< Status register.
404 #define SPI_IER_OFF 0x00000014 ///< Interrupt enable register offset.
405 #define SPI_IER (*((reg32_t *)(SPI_BASE + SPI_IER_OFF))) ///< Interrupt enable register.
406 #define SPI_IDR_OFF 0x00000018 ///< Interrupt disable register offset.
407 #define SPI_IDR (*((reg32_t *)(SPI_BASE + SPI_IDR_OFF))) ///< Interrupt disable register.
408 #define SPI_IMR_OFF 0x0000001C ///< Interrupt mask register offset.
409 #define SPI_IMR (*((reg32_t *)(SPI_BASE + SPI_IMR_OFF))) ///< Interrupt mask register.
411 #define SPI_RDRF 0 ///< Receive data register full.
412 #define SPI_TDRE 1 ///< Transmit data register empty.
413 #define SPI_MODF 2 ///< Mode fault error.
414 #define SPI_OVRES 3 ///< Overrun error status.
415 #define SPI_ENDRX 4 ///< End of RX buffer.
416 #define SPI_ENDTX 5 ///< End of TX buffer.
417 #define SPI_RXBUFF 6 ///< RX buffer full.
418 #define SPI_TXBUFE 7 ///< TX buffer empty.
419 #define SPI_NSSR 8 ///< NSS rising.
420 #define SPI_TXEMPTY 9 ///< Transmission register empty.
421 #define SPI_SPIENS 16 ///< SPI enable status.
425 * SPI Chip Select Registers
428 #define SPI_CSR0_OFF 0x00000030 ///< Chip select register 0 offset.
429 #define SPI_CS0 (*((reg32_t *)(SPI_BASE + SPI_CSR0_OFF))) ///< Chip select register 0.
430 #define SPI_CSR1_OFF 0x00000034 ///< Chip select register 1 offset.
431 #define SPI_CS1 (*((reg32_t *)(SPI_BASE + SPI_CSR1_OFF))) ///< Chip select register 1.
432 #define SPI_CSR2_OFF 0x00000038 ///< Chip select register 2 offset.
433 #define SPI_CS2 (*((reg32_t *)(SPI_BASE + SPI_CSR2_OFF))) ///< Chip select register 2.
434 #define SPI_CSR3_OFF 0x0000003C ///< Chip select register 3 offset.
435 #define SPI_CS3 (*((reg32_t *)(SPI_BASE + SPI_CSR3_OFF))) ///< Chip select register 3.
437 #define SPI_CPOL 0 ///< Clock polarity.
438 #define SPI_NCPHA 1 ///< Clock phase.
439 #define SPI_CSAAT 3 ///< Chip select active after transfer.
440 #define SPI_BITS 0x000000F0 ///< Bits per transfer mask.
441 #define SPI_BITS_8 0x00000000 ///< 8 bits per transfer.
442 #define SPI_BITS_9 0x00000010 ///< 9 bits per transfer.
443 #define SPI_BITS_10 0x00000020 ///< 10 bits per transfer.
444 #define SPI_BITS_11 0x00000030 ///< 11 bits per transfer.
445 #define SPI_BITS_12 0x00000040 ///< 12 bits per transfer.
446 #define SPI_BITS_13 0x00000050 ///< 13 bits per transfer.
447 #define SPI_BITS_14 0x00000060 ///< 14 bits per transfer.
448 #define SPI_BITS_15 0x00000070 ///< 15 bits per transfer.
449 #define SPI_BITS_16 0x00000080 ///< 16 bits per transfer.
450 #define SPI_BITS_LSB 4 ///< Least significant bit of bits per transfer.
451 #define SPI_SCBR 0x0000FF00 ///< Serial clock baud rate mask.
452 #define SPI_SCBR_LSB 8 ///< Least significant bit of serial clock baud rate.
453 #define SPI_DLYBS 0x00FF0000 ///< Delay before SPCK mask.
454 #define SPI_DLYBS_LSB 16 ///< Least significant bit of delay before SPCK.
455 #define SPI_DLYBCT 0xFF000000 ///< Delay between consecutive transfers mask.
456 #define SPI_DLYBCT_LSB 24 ///< Least significant bit of delay between consecutive transfers.
459 #endif /* AT91_US_H */